MT8888CE Zarlink Semiconductor, MT8888CE Datasheet
MT8888CE
Specifications of MT8888CE
Available stocks
Related parts for MT8888CE
MT8888CE Summary of contents
Page 1
... V DD Ref SS Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. MT8888CE MT8888CS MT8888CN MT8888CP The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling ...
Page 2
... D0-D3 Microprocessor Data Bus. High impedance when TTL compatible. MT8888C IN VDD 2 23 IN- St/ ESt 21 4 VRef VSS OSC1 OSC2 TONE 15 10 IRQ/ RS0 24 PIN SSOP Figure 2 - Pin Connections Description /2 Zarlink Semiconductor Inc. Data Sheet VRef VSS OSC1 OSC2 PIN PLCC ...
Page 3
... The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. MT8888C Description frees the device to accept a new tone pair. TSt /2. Provision is made for connection of a feedback resistor to the op Zarlink Semiconductor Inc. Data Sheet TSt ...
Page 4
... MT8888C VOLTAGE GAIN ( Figure 3 - Single-Ended Input Configuration DIFFERENTIAL INPUT AMPLIFIER 100 60k , (R2R5)/(R2 + R5) VOLTAGE GAIN (A diff) - R5/R1 V INPUT IMPEDANCE diff ( Figure 4 - Differential Input Configuration 4 Zarlink Semiconductor Inc. Data Sheet IN+ IN Ref MT8888C IN+ IN Ref MT8888C ...
Page 5
... 1633 1633 1633 reaches the threshold (V GTP continues to drive high as long as ESt remains high. Finally, after Zarlink Semiconductor Inc. Data Sheet the steering logic to register the TSt ...
Page 6
... The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): MT8888C DD MT8888C St/GT ESt (R1C1 GTA (R1C1 GTP DD Figure 5 - Basic Steering Circuit REC DPmax GTPmax DAmin REC DPmin GTPmin DAmax DAmax GTAmax DPmin DAmin GTAmin DPmax 6 Zarlink Semiconductor Inc. Data Sheet ) TSt - TSt ...
Page 7
... GTP C1 GTA (R1R2) / ( decreasing tGTA; (tGTP > tGTA) Figure 6 - Guard Time Adjustment The call progress tone input and DTMF input are common, 7 Zarlink Semiconductor Inc. Data Sheet -V )] TSt /V ) TSt -V )] TSt /V ) TSt is the minimum signal duration REC GTP with a long t REC ) ...
Page 8
... DECODED TONE # (n- Read Status Register IRQ/CP LEVEL (dBm) -25 MT8888C REC ID TONE TONE # GTP t GTA t PStRX # n t PStb3 Figure 7 - Receiver Timing Diagram 0 250 500 FREQUENCY (Hz) = Reject = May Accept = Accept Figure 8 - Call Progress Response 8 Zarlink Semiconductor Inc. Data Sheet TONE # TSt # ( 750 ...
Page 9
... The divider output clocks another counter, which addresses the sinewave lookup ROM. MT8888C Figure 9 - Description of Timing Events and f LOW 9 Zarlink Semiconductor Inc. Data Sheet ) are referred to as Low Group and HIGH ...
Page 10
... MT8888C Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 10 - Spectrum Plot 10 Zarlink Semiconductor Inc. Data Sheet ...
Page 11
... .... fundamental .... V as measured on the output waveform. The total the sum of all the intermodulation components. The IMD .... IMD Zarlink Semiconductor Inc. Data Sheet %ERROR +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73 and V correspond to the low group H ...
Page 12
... A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers. MT8888C MT8888C MT8888C OSC1 OSC2 Figure 13 - Common Crystal Connection 12 Zarlink Semiconductor Inc. Data Sheet MT8888C OSC1 OSC2 ...
Page 13
... Read from Receive Data Register 0 1 Write to Control Register 1 0 Read from Status Register Table 3 - nternal Register Functions IRQ CP/DTMF Table 4 - CRA Bit Positions C/R S/D TEST Table 5 - CRB Bit Positions DESCRIPTION 13 Zarlink Semiconductor Inc. Data Sheet b0 TOUT b0 BURST ENABLE ...
Page 14
... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. 14 Zarlink Semiconductor Inc. Data Sheet STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. ...
Page 15
... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8888C can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 15 Zarlink Semiconductor Inc. Data Sheet ...
Page 16
... DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms). MT8888C 5.0 VDC 2.4 k TEST POINT MMD7000 (or equivalent) Figure 16 - Test Circuits INITIALIZATION PROCEDURE Control RS0 RS0 Figure 17 - Application Notes 16 Zarlink Semiconductor Inc. Data Sheet 5.0 VDC 3 k 100 pF Test load for IRQ/CP pin Data ...
Page 17
... TSt V 0.1 OLO V 4.9 OHO 2.4 2.5 2.6 Ref -1.4 -6 2.0 4 Zarlink Semiconductor Inc. Data Sheet Min Max Units 6 V -0 -65 +150 1000 mW Max Units Test Conditions 5.25 V +85 C MHz Units Test Conditions Note 9* V Note =5V DD ...
Page 18
... Sym Min Typ Max I 100 PSRR 50 CMRR VOL BW 1 100 1 unless otherwise stated. ‡ Sym Min Typ -29 27.5 18 Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions mA V =4. =0. =0.4V OL Units Test Conditions kHz 20p L MHz C = 20p L -0 100 PM>40 ...
Page 19
... Typ f 310 A f 290 LR f 540 HR -30 ‡ Sym Min Typ t 40 REC t 20 REC Zarlink Semiconductor Inc. Data Sheet Units Notes* dB 2,3,6,9 dB 2,3,6,9 2,3,5 2,3,5 dB 2,3,4,5,9,10 dB 2,3,4,5,7,9,10 dB 2,3,4,5,8,9 Max Units Conditions 500 Hz @ -25 dBm, Note -25 dBm Hz @ -25 dBm dBm Max ...
Page 20
... CYC DHR t 100 DDR t 150 PWL t 100 PWH t 45 DSW 20 Zarlink Semiconductor Inc. Data Sheet Units Conditions ms Note 11 ms Note 11 s See Figure 7 s See Figure 7 ms DTMF mode ms DTMF mode ms Call Progress mode ms Call Progress mode dBm R =10k L dBm R =10k L ...
Page 21
... For guard time calculation purposes. RD/WR RD CS, RS0 DATA BUS Figure 19 - 8031/8051/8085 Read Timing Diagram MT8888C ‡ Sym Min Typ t 10 DHW OUT t CYC PWH Figure 18 - RD/WR Clock Pulse t PWL DHR DDR 21 Zarlink Semiconductor Inc. Data Sheet Max Units Conditions ns Figures 19 & PWL t PWH ...
Page 22
... CS, RS0 DATA BUS Figure 20 - 8031/8051/8085 Write Timing Diagram MT8888C t PWL t PWH DSW DHW 22 Zarlink Semiconductor Inc. Data Sheet ...
Page 23
...
Page 24
...
Page 25
...
Page 26
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...