IDT77310 Integrated Device Technology, Inc., IDT77310 Datasheet
IDT77310
Specifications of IDT77310
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IDT77310 Summary of contents
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... The part can also be used as a building block for low-cost non-blocking crosspoint switches. (See APPLICATION EXAMPLES.) Each IDT77310 has five ATM UTOPIA interface ports. Ports and D are byte-wide UTOPIA Level 1 ports while Port programmable byte- or word-wide UTOPIA Level 2–compatible port. Data parity bit transfers are also supported, one parity bit for each byte if bit 6 of the configuration register is set to “ ...
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... IDT77310 PRELIMINARY rty_A ata ata ata ata ta_ ta_ ata ata TxC TxSO rty_A 16 TxD a ta_ TxD a ta_ ata ata ata ata TxD a ta_ TxD a ta_ xClk_W 29 RxClav_A lav_A ata ta_ W [ ta_ W [ ta_ W [ ata ata ata_W [ ata ata ata ata 1999 Integrated Device Technology, Inc ...
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... LOW-COST ATM SWITCH BUILDING BLOCK By feeding the output of the multiplexer portion of the IDT77310 back into the demultiplexer portion, and adding some external logic to control the UTOPIA bus and port addressing, the device becomes a switch capable of switching any input port to any output port (see Figure 5) ...
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... The same type of switch, implemented with the fanout technique shown in Figure 4, requires only one crosspoint chip and four IDT77310 mux/demux chips, providing the function the pricey crosspoint chips for the cost of only four less expensive mux/demux chips. Besides the obvious cost savings of this technique, the mux/demux I/O ring ...
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... W data lines of several chips together, as shown in Figure eight devices can be paralleled in this way. With a combination of mux/demux width expansion, a bit of UTOPIA bus controller logic, and (optional) external buffering, the IDT77310 can be used in access equipment, such as the workgroup switch shown in Figures 7 and 8. Port A ...
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... IDT77310 PRELIMINARY 1 1 Notes: 1. Provides 12 ports with local switching with 51.84-Mb/s per port full duplex. 2. Connects workgroup ATM switch fabric via 622-Mb/s OC12 line (Uplink Port). 3. 51.84-Mb/s bandwidth available for each of 12 ports (OC1-compatible). 4. Input and output FIFO buffering: – Inputs: four cells per port. ...
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... IDT77310 PRELIMINARY Notes: 1. Provides 24 ports with local switching at 25-Mb/s per port full duplex. 2. 25-Mb/s bandwidth available for each of 24 ports (ATM 25-compatible). 3. Connects workgroup to ATM switch fabric via 622-Mb/s OC12 line (Uplink Port). 4. Input and output FIFO buffering. – Inputs: four cells per port. ...
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... IDT77310 PRELIMINARY OC3-TO-OC12 LINE CONCENTRATOR With the addition of SONET Framer and physical layer interface (PHY), the IDT77310 can concentrate 51.84-Mb/s OC1 and 155-Mb/s OC3 lines into 622-Mb/s OC12 lines, as shown in Figures 9 and 10, respectively. OC1 PHY FRAMER (1) OC1 PHY (2) FRAMER OC1 PHY ...
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... IDT77310 PRELIMINARY RxXXX_A RxData_A RxXXX_B RxData_B RxXXX_C RxData_C RxXXX_D RxData_D SWFF R/W Controls D[7:0]/A[2:0] SDA TxXXX_A TxData_A TxXXX_B TxData_B TxXXX_C TxData_C TxXXX_D TxData_D Notes: • RxXXX = RxClk, RxSOC, RxClav and RxEnb; TxXXX = TxClk, TxSOC, TxClav and TxEnb. • RxData_X and TxData_X and D are 9 bits wide, including a parity bit. RxData_W and TxData_W are 18 bits wide, including two parity bits bits wide including one parity bit. • ...
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... IDT77310 PRELIMINARY The IDT77310 I/O signals are listed in Table 1 in incremental pin number order. Definitions of these signals are presented in Tables 2, 3, and 4, grouped according Table 1. IDT77310 Pin Numbers and Signal Descriptions Pin # Signal I/O Pin # Signal 1 RxPrty_A I 53 RxPrty_B 2 RxData_A[ RxData_B[7] ...
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... RxData_X. O Byte-wide data transmitted out of Port X. O Odd parity bit over TxData_X[7–0]. O Start Of Cell. Asserted by the IDT77310 when TxData_X contains first valid byte of a cell. O Enable. Asserted by the IDT77310 during cycles when TxData_X contains valid cell data. I Cell Available. Asserted by device connected to Port X to indicate it can accept the transfer of a complete cell ...
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... I Enable. This signal is low during cycles when TxData_W contains valid cell data. O† Cell Available. Asserted by the IDT77310 to indicate it can accept the transfer of a complete cell. This bit is tri-stated whenever TxAddr[4-0] does not match the port addresses assigned to the device. I Data transfer clock input to the IDT77310 for synchroniz- ing transfers on TxData_W ...
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... I 5V power supplies. I Ground. Data transfers in or out of the IDT77310 are carried out in whole cell units, where one cell equals data bytes data words (dual-byte), as determined by the cell-length register setting. Following the UTOPIA convention, data is said to be transmitted from Port W to Ports and received from Ports Port W ...
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... Port A, Port B, Port C, or Port D. If the difference between PAL and PAH is less than 3, one or more of the IDT77310’s ports are not accessible. This feature can be used to configure the IDT77310 as a 2:1, 3:1, or 4:1 multiplexer/ demultiplexer. If PAH is lower than PAL, the IDT77310 will not function. If PAH is higher than PAL by more than 3, undefined states may exist and the IDT77310 will function unpredictably ...
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... VCL Variable Cell Length. Setting this bit to “1” changes the length of a cell used in the IDT77310 operation from the standard 53 bytes (in 8-bit mode words (in 16-bit mode length defined by bit 7 to bit 5 of the PMA register. Default of this bit is “0,” which specifies a cell length of the standard 53 bytes or 27 words ...
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... IDT77310 PRELIMINARY STATUS REGISTER The Status register holds status information on the two FIFOs in Port read-only register. The register’s bit definitions are shown in Figure 16. SWFF and SDA read the inverse binary value of pins 103 and 102, Bit 7 Reserved Reserved Notes: SWFF System Write FIFO Full flag. This bit has the same definition as the output pin of the same name. This bit is set to “0” when the Port M receiving FIFO is full from a system write operation and it remains so until one full cell is transferred out of the FIFO. The bit is then set to “ ...
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... IDT77310 PRELIMINARY a. Bits 7-6: Mode B7 B6 Mode 0 0 Normal operation (default Port W loopback 1 0 Port X loopback 1 1 Undefined b. Bits 5-3: Port X Loopback Input Port Select Bits 2-0: Port X Loopback Output Port Select 1999 Integrated Device Technology, Inc Input Port Port A (default) ...
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... If the transmitted data is destined for Port M’s system FIFO, the IDT77310 sets the SDA flag low as soon as a full cell is stored into the FIFO, to indicate there is data in the IDT77310 for the host to retrieve. ...
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... FIFO while continuously accepting transmitted data from Port W. Similarly, while receiving a data stream longer than one cell from Ports Port M, the IDT77310 is capable of starting a receive transfer at Port W after one full cell is stored in the source port’s receiving FIFO. ...
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... IDT77310 PRELIMINARY 1 RxPrty_A 51 RxData_B[1] 2 RxData_A[7] 52 RxData_B[0] RxEnb_B 3 RxData_A[ RxData_A[5] 54 RxClk_B TxEnb_B 5 RxData_A[ RxData_A[3] 56 TxClk_B 7 RxData_A[2] 57 TxSOC_B 8 RxData_A[1] 58 TxPrty_B 9 RxData_A[0] 59 TxData_B[7] RxEnb_A 10 60 TxData_B[6] 11 RxClk_A 61 TxData_B[5] TxEnb_A 12 62 TxData_B[4] 13 TxClk_A 63 TxData_B[3] 14 TxSOC_A 64 TxData_B[2] 15 TxPrty_A 65 TxData_B[1] 16 TxData_A[7] 66 TxData_B[0] 17 TxData_A[6] 67 RxSOC_B 18 TxData_A[5] 68 RxClav_B 19 TxData_A[4] ...
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... TDO. The ID register consists of a chain of 32 1-bit ID cells that are hard-wired with the device’s ID code. To read the ID code, enter the Shift-DR state and insert “0” (or any dummy value) 32 times. The ID code will be shifted out of TDO for examination. The ID code for the IDT77310 is 168101D3h, or “0001-0110-1000-0001-0000-0001-1101-0011” in binary code. ...
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... IDT77310 PRELIMINARY Symbol Parameter I Dynamic Power Supply Current CCD Description Applies to Input Capacitance All input pins Tri-stated Output All tri-stateable outputs and I/O pins Description TxClk_W frequency TxClk_W duty cycle Output delay from TxClk_W going high to TxClav_W valid Input setup from signal valid to ...
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... IDT77310 PRELIMINARY Description RxClk_X frequency RxClk_X duty cycle Output delay from RxClk_X going high to signal valid Input setup from signal valid to RxClk_X going high Input hold from RxClk_X going high to signal invalid Symbol Description READ Cycle t Read Cycle Time RC t Address Access Time ...
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... IDT77310 PRELIMINARY WP/ (1) RxPrty_X(In (2) RxPrty_W (Out RxPrty_W (Out TxPrty_X (Out TxPrty_W (In TxPrty_W (In RxPrty_X(A,B) (Byte Parity) TxPrty_X(A,B) (Byte Parity) Notes: 1. WP/BP = Word Parity/Bit Parity, and refers to bit #6 of the Configuration Register. When this bit is set to “0” (Default) the one parity bit per byte mode is selected. When it is set to “ ...
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... IDT77310 PRELIMINARY TxClk TxAddr N+1 1F N+2 1F TxClav N+1 N+2 TxEnb* TxData P35 P36 P37 P38 TxSOC TxClk TxAddr 1F N+1 1F N+2 1F TxClav N+1 N+2 TxEnb* TxData P45 P46 P47 P48 TxSOC PHY N TxClk_X TxSOC_X TxClav_X TxEnb_X TxData_X 1999 Integrated Device Technology, Inc ...
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... IDT77310 PRELIMINARY RxClk RxAddr N+1 1F N+2 1F RxClav N+1 N+2 RxEnb* RxData P35 P36 P37 RxSOC RxClk RxAddr 1F N+1 1F N+2 RxClav N+1 RxEnb* RxData P41 P42 P45 P44 RxSOC PHY N 1999 Integrated Device Technology, Inc N+3 1F N+1 1F N+2 1F N+3 1F N+3 N+1 N+2 ...
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... IDT77310 PRELIMINARY CONFIGURATION REGISTER BIT # (DEFAULT) RxClk_X RxCLAV_X RxEnb_X RxSOC_X RxData_X RxCLAV_X RxEnb_X RxSOC_X RxData_X RxCLAV_X RxEnb_X RxSOC_X RxData_X RxCLAV_X RxEnb_X RxSOC_X RxData_X CONFIGURATION REGISTER BIT # RxClk_X RxCLAV_X RxEnb_X RxSOC_X RxData_X 1999 Integrated Device Technology, Inc P45 P46 P47 P48 H1 H2 ...
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... IDT77310 PRELIMINARY A[2: CLZ D[7:0] SDA A[2: CCS WR "HIGH" OE D[7:0] SWFF 1999 Integrated Device Technology, Inc t AA ADDRESS VALID t ACS OLZ t OS ADDRESS VALID OHZ t CHZ DATA VALID DATA VALID IDT DSC-XXXXXX ...
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... IDT77310 PRELIMINARY TxClk_W RxClk_W Reset TxClk_W TxSOC_W TxClav_W TxEnb_W X X TxData_W RxClk_W RxSOC_W RxClav_W RxEnb_W RxData_W X 1999 Integrated Device Technology, Inc t RS H1/H2 H3/H4 UD1/2 P1/P2 P45/P46 P47/P48 X X H1/H2 H3/ RTC t RRC 5354drw22 X H1/H2 H3/H4 P43/P44 P45/P46 P47/P48 X H1/ IDT DSC-XXXXXX ...
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... IDT77310 PRELIMINARY PLASTIC QUAD FLATPACK PACKAGE Counterclockwise orientation, top view Notes: 1. Refer to applicable symbol list. 2. All dimensions are in millimeters, unless otherwise specified. 3. Dimensions D and E do not include mold protrusions. Allowable mold protrustions are: D and E = 0.25mm Max and NE represent number of leads in D and E directions, respectively ...
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... IDT77310 PRELIMINARY IDT XXXXX Device Type The attached document is the property of Integrated Device Technologies, Inc preliminary engineering product specification and does not imply or guarantee offer of this product by Integrated Device Technologies, Inc. in the future. Integrated Device Technologies, Inc. does not assume any responsibility for design or designs done based on the description in this document. No patent or other license is conveyed or implied by this document and Integrated Device Technologies, Inc ...