IDT71V3578S133BG Integrated Device Technology, Inc., IDT71V3578S133BG Datasheet

IDT71V3578S133BG

Manufacturer Part Number

IDT71V3578S133BG

Description

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT71V3578S133BG.pdf (23 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

IDT71V3578S133BG

Manufacturer:

IDT

Quantity:

20 000

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NOTE:

1. BW

CLK

I/O

BWE

ADV

ADSC

ADSP

LBO

-A

128K x 36, 256K x 18 memory configurations

Supports high system speed:

Commercial and Industrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

-I/O

, CS

, V

, BW

DDQ

and BW

, I/O

, BW

-I/O

, BW

are not applicable for the IDT71V3578.

(1)

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Address Inputs

Address Status (Cache Controller)

Address Status (Processor)

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

system designer, as the IDT71V3576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the LBO input pin.

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

The IDT71V3576/78 are high-speed SRAMs organized as

The burst mode feature offers the highest level of performance to the

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

Supply

Input

I/O

Asynchronous

Synchronous

IDT71V3576

IDT71V3578

N/A

DSC-5279/02

5279 tbl 01

Related parts for IDT71V3578S133BG

IDT71V3578S133BG Summary of contents

Page 1

... NOTE and BW are not applicable for the IDT71V3578 ©2003 Integrated Device Technology, Inc. 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data, address and control registers ...

Page 2

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Pin Function I Address Inputs ADSC Address Status I (Cache Controller) ADSP Address ...

Page 3

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect LBO ADV CLK ADSC ADSP 16/17 GW BWE ...

Page 4

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to ...

Page 5

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 100 I I I/O 3 ...

Page 6

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I ...

Page 7

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ G I/O ...

Page 8

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect ( I/O NC ...

Page 9

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I | LZZ |I | ...

Page 10

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected ...

Page 11

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H ...

Page 12

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width ...

Page 13

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...

Page 14

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 14 ...

Page 15

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

Page 16

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 17

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 18

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input ...

Page 19

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...

Page 20

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...

Page 21

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...

Page 22

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect IDT XXX Device Power Speed Package Type X Process/ Temperature Range Blank Commercial (0°C to +70°C) ...

Page 23

... Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 04/22/03 Pg.4 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Updated to new format Revised I and I for speeds 100–200MHz SB1 ZZ Revised t (min.) at 166MHz CDC Added 119 BGA package diagram ...

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