CXD3059AR Sony, CXD3059AR Datasheet

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CXD3059AR

Manufacturer Part Number
CXD3059AR
Description
CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
Manufacturer
Sony
Datasheet

Specifications of CXD3059AR

Case
QFP

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Description
players. This LSI incorporates a RF amplifier and digital servo,
high & bass boost, 1-bit DAC and analog low-pass filter.
Features
• All digital signal processing during playback is performed with
• Highly integrated mounting possible due to a built-in RF
RF Block
• Supports 4 speed playback CD
• RF system equalizer
• Supports pickup built-in RF summing amplifier
• Gain level switch
• TE balance adjustment function
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated by
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and subcode-Q data error detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from CPU
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages,
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
• Independent turnover frequency selection possible
The CXD3059AR is a digital signal processor LSI for CD
a single chip
amplifier
• Frame jitter free
• 0.5 to 4 speed continuous playback possible
• Allows relative rotational velocity readout
the digital PLL.
C1: double correction, C2: quadruple correction
Supported during 4 speed playback
interface
Focus filter: 5 stages
CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
Bass Boost: 4th-order IIR 24dB/Oct
High Boost: Second-order IIR 12dB/Oct
Bass Boost: 125Hz/160Hz/200Hz
High Boost: 5kHz/7kHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
+10dB/+14dB/+18dB/+22dB
+4dB/+6dB/+8dB/+10dB
– 1 –
• Digital dynamics (compressor)
• 8 oversampling digital filter
• Digital signal output possible after boost
• Serial data format selectable from (output)
• Digital attenuation: – , –60 to +6dB, 2048 steps (linear)
• Soft mute
• Digital de-emphasis
• High-cut filter
Applications
Structure
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage 1
• Input voltage 1
• Output voltage 1
• Supply voltage 2
• Input voltage 2
• Output voltage 2
• Storage temperature
• Supply voltage difference
Recommended Operating Conditions
• Supply voltage 1
• Supply voltage 2
• Operating temperature
I/O Pin Capacitance
• Input capacitance
• Output capacitance C
• I/O capacitance
Note) Measurement conditions V
Volume increased by +5dB at low level
(attenuation: 61dB, ripple within band: ±0.0075dB)
20 bits/18 bits/16 bits (rearward truncation, MSB first)
CD players
Silicon gate CMOS IC
CXD3059AR
120 pin LQFP (Plastic)
V
V
V
IOV
V
V
Tstg
IOV
XV
IOV
V
IOV
Topr
C
C
DD
I
O
I
O
DD
I
O
I/O
1
2
1
2
DD
DD
, XV
DD
SS
, XV
DD
, AV
0 to 2, AV
– V
, AV
0 to 2, AV
DD
DD
(IOV
IOV
IOV
DD
SS
DD
f
V
V
M
, XV
DD
, XV
IOV
SS
SS
SS
SS
DD
= 1MHz
V
= V
SS
, AV
– 0.3 to V
– 0.3 to V
– 0.3 to IOV
– 0.3 to IOV
DD
DD
SS
–55 to +150
SS
–0.3 to +0.3
–0.3 to +0.3
–0.3 to +0.3
DD
–20 to +75
2.5 ± 0.2
3.3 ± 0.3
– 0.5 to +3.5
7 (Max.)
7 (Max.)
7 (Max.)
0 to 5
0 to 5
I
– 0.5 to +4.5
– V
DD
– V
= 0V
, XV
SS
DD
DD
DD
DD
E03736-PS
DD
DD
+ 0.3
+ 0.3
< 2.3V)
+ 0.3 V
+ 0.3 V
pF
pF
pF
°C
°C
V
V
V
V
V
V
V
V
V

Related parts for CXD3059AR

CXD3059AR Summary of contents

Page 1

... CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost Description The CXD3059AR is a digital signal processor LSI for CD players. This LSI incorporates a RF amplifier and digital servo, high & bass boost, 1-bit DAC and analog low-pass filter. ...

Page 2

... LPF DAC CD Signal Clock Prosessor Generator Block Digital OUT Selector D/A Interface 32K RAM EFM Demodulator Digital DC/DC PLL Convertor CXD3059AR LMUT RMUT AOUT2 VREFR VREL AOUT1 EMPHI LRCKI PCMDI BCKI XTACN XTSL XTAI XTAO VCTL VPCO DOUT BCK PCMD LRCK ...

Page 3

... ATSK 109 WFCK 110 XUGF 111 112 XPCK 113 GFS 114 C2PO 115 SCOR V 116 DD C4M 117 WDCK 118 COUT 119 120 – 3 – CXD3059AR 60 BCKI DDCR DDVRSEN 55 DDVROUT PCO 52 FILI 51 FILO 50 CLTV VCTL 47 VPCO 46 ASYO 45 ASYI 44 BIAS RFACI 41 RFACO RFC ...

Page 4

... Center voltage input to DSSP block by command switch. A signal input. B signal input. C signal input. D signal input. — — Analog power supply. RFDC signal output. RFDC signal input to DSSP block by command switch. Reference voltage pin for PD. Analog RFAC summing amplifier output. – 4 – CXD3059AR Description ...

Page 5

... D/A interface serial data output (2's COMP, MSB first D/A interface bit clock output. — Internal digital power supply High when the playback disc has emphasis, low it has not. High when de-emphasis is ON, low when input OFF. – 5 – CXD3059AR Description , High = ...

Page 6

... Subcode serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. — Internal digital GND. Latch input from CPU. The serial data is latched at the falling edge. – 6 – CXD3059AR Description ...

Page 7

... High output when the subcode sync S1, is detected. — Internal digital power supply. 4.2336MHz output 1/4 frequency-division output of the V16M in CAV-W mode and variable pitch mode. Word clock output 2Fs GRSCOR output by command switch Track number count signal input/output. — – 7 – CXD3059AR Description ...

Page 8

... Power on with XRST pin low. Set XRST pin high after holding it low 100ns or more to cancel reset. MTSL0 0 XUGF 1 MNT0 0 RFCK 1 C4M 0 SOUT – 8 – Output data XPCK GFS MNT1 MNT2 XPCK XROF GSTO GFS SOCK XOLT CXD3059AR C2PO MNT3 GTOP C2PO C2PO ...

Page 9

... VC I/O Equivalent circuit 1pF 22 23 1pF 24 25 – 9 – CXD3059AR Description Tracking error amplifier input. Tracking error signal input to DSSP block. Tracking error amplifier output. Focus error signal input to DSSP block. Focus error amplifier output. (AV 4 – AV 4)/2 voltage output ...

Page 10

... Equivalent circuit 15k 30k 30k — — 10k 0.5pF 100 32 59k 10k 33 34 – 10 – CXD3059AR Description RF summing amplifier and focus error amplifier input. — Analog power supply. RFDC amplifier output. APC amplifier reference voltage (GND signal) input. RFAC summing amplifier output. ...

Page 11

... Pin Symbol I/O No. 35 EQ_IN — 39 RFC — RFACO O Equivalent circuit 57k 10k 500 — 39 — – 11 – CXD3059AR Description Equalizer circuit input. APC amplifier output. APC amplifier input. — Equalizer cut-off frequency adjustment. Analog GND. RFAC amplifier output. ...

Page 12

... –1.2mA ( 2mA –2.4, –4. (3) OH –7.2, –9.6mA V ( 12, 16mA ( –0.28mA ( 0.36mA – 12 – IOV = Min. Typ. Max. Unit 0. 0.2V DD 0. – 0 0.4 V – 0 0.4 V – 0 0.4 V – 0 0.4 –10 10 µA 40 100 240 µA –10 10 µA CXD3059AR Applicable pins ...

Page 13

... SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SQSO, SBSO, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK 6 ASYO 7 DOUT 8 MDP, VPCO, PCO, SENS 9 MIRR, DFCT, FOK, LOCK, ATSK, COUT 10 TEO, FEO, AC_SUM, LD, RFACO, DDVROUT, AOUT1, VREFL, VREFR, AOUT2 11 FILO 12 VC, RFDCO – 13 – CXD3059AR ...

Page 14

... V DD Min. Typ. Max. Unit 6.6 32.7 ns 6.6 32.7 ns 14.6 59.5 ns 1 WLX V IHX V IHX IHX V ILX – 14 – IOV = Min. Typ. Max. 16.8 16.9344 17.1 33.5 33.8688 34.2 67.1 67.7376 68 IOV = 0.9 0.1 CXD3059AR Unit MHz ...

Page 15

... T SBSO SQSO 3.3 ± 0.3V Symbol Min. Typ 62.5 WCK t 300 SU t 300 H t 300 D t 750 750 750 7 WCK – 15 – IOV = Max. Unit 16 MHz 30000 30000 ns ns 0.65 MHz ns 0.65 MHz 120000 ns 65 kHz µs t WSC CXD3059AR ...

Page 16

... SCLK MSB 3.3 ± 0.3V Min. Typ. Max. SCLK 31.3 SPW 15 DLS 3.3 ± 0.3V Symbol Min COUT f 40 MIRR f 5 DFCTH 0.23V DD – 16 – IOV = Unit 16 MHz ns µ IOV = Typ. Max. Unit Conditions kHz kHz kHz CXD3059AR LSB = 0V ...

Page 17

... LPF external circuit diagram RF CXD3059AR 3.3V Min. Typ. Max. 920 928 OUT VREF – 17 – = IOV = AV = 0V, Topr = +25° Min. Typ. 0.006 90 95 Audio Analyzer Rch A Audio Analyzer Lch B = IOV = AV = 0V, Topr = +25° Unit Applicable pins 1 mVrms µF CXD3059AR Max. Unit 0.014 % dB ...

Page 18

RF Block Electrical Characteristics ( 2.5V, IOV 3.3V Sending Measurement item Symbol conditions command Connect to Input impedance VC except R A,B,C,D ...

Page 19

SW Sending Measurement item Symbol conditions command Input voltage V IR-ACSUM range Output voltage V OR-ACSUM range Input conversion V $3AA000 OF-ACSUM DC offset voltage Input conversion DC offset V $3AA01C DF-ACSUM temperature drift Offset voltage V OFFSUM Frequency F ...

Page 20

SW Sending Measurement item Symbol conditions command Input voltage V IR-FE range Output voltage V OR-FE range Input conversion V OF-FE DC offset voltage Input conversion DC offset V DF-FE temperature drift Offset voltage V OFFFE Frequency F $3AA104 FE1 ...

Page 21

SW Sending Measurement item Symbol conditions command Input voltage V IR-EQ range Output voltage V OR-EQ range Input conversion V OF-EQ DC offset voltage Input conversion DC offset V DF-EQ temperature drift Offset voltage V OFFEQ Frequency F $3AA204 EQ1 ...

Page 22

... Use the bypass condenser C with capacitance led by resistance (regulator output impedance and wiring resistance more seeing the figure bellow. Regulator GND AVS 0.1µ 15k less. 20mm, L2 20mm and OUT 0.1µF Impedance R tolerance for bypass condenser C L4 RFC – 22 – CXD3059AR 40mm [µF] 100 ...

Page 23

... When it is 400ms or more necessary to enlarge the value 3.3 ± 0.3V Conditions Min. — — DDVROUT DDCR DC-DC converter application circuit sample – 23 – IOV = Typ. Max. Unit 2.3 2.5 2.7 V — — 100 mA VOUT CXD3059AR = 0V, ...

Page 24

... TRDR D18 D19 D20 n 236 (ns Output value – A 64t MCK At MCK 32t 32t MCK MCK t MCK MCK 2 2 – 24 – D21 D22 D23 750ns or more Valid Deceleration Deceleration Output value 0 64t MCK 32t 32t MCK MCK t MCK CXD3059AR Z Z 32t MCK ...

Page 25

... L14 L13 L12 L11 L10 L14 L13 L12 L11 L10 L16 L15 L14 L13 L12 L11 L10 L18 L17 L16 L15 L14 L13 L12 L11 L14 L13 L12 L11 L10 – 25 – CXD3059AR 24 32 L10 Rch MSB Rch MSB Rch MSB Rch MSB Rch MSB ...

Page 26

... Driver circuit – 26 – BCK PCMD LRCK BCKI NC 59 DDCR DDVRSEN 55 DDVROUT PCO 53 52 FILI 51 FILO CLTV VCTL 48 47 VPCO 46 ASYO ASYI 45 BIAS RFACI RFACO RFC Driver circuit EQ_IN 35 AC_SUM 34 33 PDSENS RFDCO RFDCO CXD3059AR DDVROUT PD LD A.GND SLED SPDL Limit switch ...

Page 27

... LQFP (PLASTIC) 18.0 ± 0.2 16.0 ± 0.20 ± 0.03 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL LQFP-120P-L01 LEAD TREATMENT LQFP120-P-1616 LEAD MATERIAL PACKAGE MASS – 27 – 1.7 MAX 1.4 ± 0 EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.8g Sony Corporation CXD3059AR ...

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