IDT71V3557 Integrated Device Technology, Inc., IDT71V3557 Datasheet

IDT71V3557

Manufacturer Part Number

IDT71V3557

Description

3.3V 128Kx36 ZBT Synchronous Flow-Through SRAM with 3.3V I/O

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT71V3557.pdf (28 pages)

Specifications of IDT71V3557

Case

QFP

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Download datasheet (512Kb)

bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT

cycle, and on the next clock cycle the associated data cycle occurs, be

R/W

CLK

I/O

CEN

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

-A

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

cycles

Internally synchronized output buffer enable eliminates

the need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

Address and control signals are applied to the SRAM during one clock

-I/O

, V

, CE

, BW

DDQ

, I/O

, CE

, BW

Feature - No dead cycles between write and read

-I/O

, BW

, or Zero Bus Turnaround.

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Linear / Interleaved Burst Order

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Address Inputs

Advance burst address / Load new address

Test Mode Select

Test Data Input

Test Clock

Test Data Output

- BW

) control (May tie active)

128K x 36, 256K x 18,

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

DDQ

)

it read or write.

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

to deselect the device when desired. If any one of these three is not asserted

when ADV/LD is low, no new memory operation can be

selected or a write is initiated.

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

their previous values.

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

The IDT71V3557/59 contain address, data-in and control signal

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

There are three chip enable pins (CE

The IDT71V3557/59 have an on-chip burst counter. In the burst

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

Supply

Output

Input

I/O

, CE

IDT71V3557SA

IDT71V3559SA

, CE

IDT71V3557S

IDT71V3559S

Asynchronous

Synchronous

) that allow the user

Static

N/A

DSC-5282/06

5282 tbl 01

Related parts for IDT71V3557

IDT71V3557 Summary of contents

Page 1

... The IDT71V3557/59 have an on-chip burst counter. In the burst mode, the IDT71V3557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence ...

Page 2

... Synchronous active high chip enable. CE polarity but otherwise identical to CE and CE 1 This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made N/A with respect to the rising edge of CLK. N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register) ...

Page 3

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs LBO Address A [0:16 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST (optional Control Logic Clk JTAG TDO (SA Version) 6.42 3 Commercial and Industrial Temperature Ranges ...

Page 4

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs LBO Address A [0:17 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST (optional) Symbol Parameter Min. V Core Supply Voltage 3.135 DD V I/O Supply Voltage 3 ...

Page 5

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs (1) Grade Temperature V SS Commercial 0°C to +70°C 0V Industrial -40°C to +85°C 0V NOTES the "instant on" case temperature. A 100 DDQ I/O ...

Page 6

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs 100 DDQ I I DDQ DDQ DDQ NOTES: 1. Pins 14, 64, and 66 do not have to be connected directly < Pin 16 does not have to be connected directly > ...

Page 7

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs DDQ I I DDQ G I DDQ K I DDQ I I DDQ DDQ I DDQ DDQ DDQ I DDQ NOTES and J5 do not have to be directly connected ...

Page 8

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ (1) ( I/O I DDQ K I/O I DDQ L I/O I DDQ M I/O I DDQ N I DDQ ( LBO R NC ...

Page 9

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs CEN CE , R/W ADV/ ( NOTES Don’t Care When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle ...

Page 10

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. ...

Page 11

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/W ADV NOTES timing transition is identical to CE signal High Low Don't Care High Impedence. ...

Page 12

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/W ADV/ n NOTES High Low Don’t Care High Impedance timing transition is identical to CE signal Cycle Address R/W ADV/LD ...

Page 13

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/W ADV NOTES High Low Don’t Care High Impedance timing transition is identical to CE signal Cycle ...

Page 14

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/W ADV NOTES High Low Don’t Care Don't Know High Impedance timing transition is identical to CE signal ...

Page 15

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Symbol Parameter |I | Input Leakage Current LI LBO, JTAG and ZZ Input Leakage Current | Output Leakage Current LO V Output Low Voltage OL V Output High Voltage ...

Page 16

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...

Page 17

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 18

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 19

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 20

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs CEN Commercial and Industrial Temperature Ranges 6. ...

Page 21

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs CS Commercial and Industrial Temperature Ranges 6. ...

Page 22

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. ...

Page 23

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Instruction EXTEST SAMPLE/PRELOAD DEVICE_ID HIGHZ RESERVED ...

Page 24

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 24 ...

Page 25

Page 26

Page 27

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs OE OE DATA Out NOTE read operation is assumed progress. IDT XXXX XX XX Device Power Speed Type t OHZ Package Process/ Temperature Range Blank ...

Page 28

... IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs 6/30/99 8/23/99 Pg Pg. 7 Pg. 15 Pg. 21 Pg. 23 12/31/99 Pg. 5, 14, 15, 22 05/02/00 Pg. 5,6 Pg. 5,6,7 Pg. 6 Pg. 21 05/26/00 Pg. 23 07/26/00 Pg. 5-8 Pg. 8 Pg. 23 10/25/00 Pg ...

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