MPC949 Motorola, MPC949 Datasheet
MPC949
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MPC949 Summary of contents
Page 1
... The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability to allow the user to select the ratio of 1X outputs to 1/2X outputs ...
Page 2
... Pullup) PCLK (Int Pulldown) PCLK (Int Pullup) Dseln (Int Pulldown) MR/OE (Int Pulldown) PCLK_Sel (Int Pulldown VCCd 24 Qd4 23 GNDd 22 Qd3 21 VCCd MPC949 20 Qd2 19 GNDd 18 Qd1 17 VCCd 16 Qd0 15 GNDd Function Select pin to choose TCKL0 or TCLK1 LVCMOS/LVTTL clock inputs True PECL clock input ...
Page 3
... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the V CMR range and the input swing lies within the V PP specification. 2. The MPC949 outputs can drive series or parallel terminated 50 ( /2) transmission lines on the incident edge (see Applications Info section). ...
Page 4
... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC949 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...
Page 5
... –M– 0.10 (0.004 VIEW 0.25 (0.010) GAGE PLANE MPC949 –X– X= VIEW Y BASE METAL F PLATING Ç Ç Ç Ç É É É É Ç Ç Ç Ç É É É É D 0.13 (0.005) T L– SECTION AB–AB ROTATED 90 _ CLOCKWISE NOTES: 1 ...
Page 6
... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 MPC949/D TIMING SOLUTIONS BR1333 — Rev 6 ...