IDT7024 Integrated Device Technology, Inc., IDT7024 Datasheet

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IDT7024

Manufacturer Part Number
IDT7024
Description
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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FEATURES:
• True Dual-Ported memory cells which allow simulta-
• High-speed access
• Low-power operation
• Separate upper-byte and lower-byte control for
• IDT7024 easily expands data bus width to 32 bits or
FUNCTIONAL BLOCK DIAGRAM
NOTES:
1. (MASTER):
2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
Integrated Device Technology, Inc.
neous access of the same memory location
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
— IDT7024S
— IDT7024L
multiplexed bus compatibility
more using the Master/Slave select when cascading
BUSY
(SLAVE):
is input.
BUSY
and
are non-tri-stated
push-pull.
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
INT
is output;
outputs
outputs
BUSY
I/O
I/O
BUSY
8L
0L
-I/O
SEM
INT
R/
-I/O
UB
A
OE
CE
LB
A
L
(1,2)
W
15L
11L
0L
L
(2)
L
7L
L
L
L
L
L
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Decoder
Address
R/
CE
OE
W
L
L
L
1 2
Control
I/O
6.15
ARBITRATION
SEMAPHORE
• M/
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
• Devices are capable of withstanding greater than 2001V
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 5V ( 10%) power supply
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
• Industrial temperature range (–40 C to +85 C) is avail-
INTERRUPT
MEMORY
ARRAY
more than one device
M/
between ports
PLCC, and 100-pin Thin Quad Plastic Flatpack
able, tested to military electrical specifications
LOGIC
electrostatic discharge.
M/
S
S
S
= H for
= L for
Control
BUSY
BUSY
I/O
1 2
input on Slave
output flag on Master
Decoder
Address
CE
OE
R/
W
R
R
R
IDT7024S/L
OCTOBER 1996
SEM
INT
BUSY
I/O
R/
UB
2740 drw 01
LB
OE
A
CE
I/O
A
11R
0R
W
R
R
8R
DSC-2740/6
R
R
(2)
R
R
0R
R
-I/O
R
-I/O
(1,2)
15R
7R
1

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IDT7024 Summary of contents

Page 1

... Active: 750mW (typ.) Standby: 5mW (typ.) — IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) • Separate upper-byte and lower-byte control for multiplexed bus compatibility • IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading FUNCTIONAL BLOCK DIAGRAM ...

Page 2

... Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500 W from a 2V battery. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84- pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability ...

Page 3

... INT L R BUSY BUSY GND (1, SEM I/O I/O I I/O I/O I GND 12L 73 V 14L CC IDT7024 G84-3 74 GND 84-PIN PGA TOP VIEW ( SEM GND GND I/O I/O I 10R 13R 15R I/O I/O 12R 14R RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Names Grade ...

Page 4

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL (1) Inputs NOTE — A are not equal to A — 11L 0R 11R. TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL Inputs NOTE: 1. There are eight semaphore flags written to via I/O ABSOLUTE MAXIMUM RATINGS Symbol ...

Page 5

... L — CC SEM > 0. 0.2V or COM S 100 CC L 100 (3) = 120mA (typ 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES (V = 5.0V 10%) CC IDT7024S IDT7024L Min. Max. Min. — 10 — CC — 10 — CC — 0.4 — 2.4 — 2.4 ( 5.0V 10%) CC 7024X17 7024X20 Com'l. Only (2) (2) Max ...

Page 6

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter CE I Dynamic Operating CC SEM Current (Both Ports Active Standby Current SB1 SEM (Both Ports — TTL Level Inputs Standby Current SB2 (One Port — TTL ...

Page 7

... To access semaphore SEM CE 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES 5V 1250 DATA OUT 775 30pF 775 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) Including scope and Jig (4) IDT7024X20 IDT7024X25 Max. Min. Max. Min. 17 — 20 — 25 — 17 — 20 — — 17 — 20 — ...

Page 8

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM WAVEFORM OF READ CYCLES ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is de-asserted first delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations ...

Page 9

... IDT7024X35 Min — (1, 2) — ( SEM access semaphore will always be smaller than the actual 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT7024X20 IDT7024X25 Max. Min. Max. Min. 17 — 20 — — 15 — — 15 — — 0 — — 15 — — 0 — ...

Page 10

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS OE ( SEM ( ( DATA (4) OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO. 2, ADDRESS CE SEM ( DATA IN NOTES & must be High during all address transitions write occurs during the overlap ( measured from the earlier During this period, the I/O pins are in the output state and input signals must not be applied. ...

Page 11

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE VALID ADDRESS t AW SEM I NOTES & for the duration of the above timing (both write and read cycle "DATA VALID" represents all I/O's (I/O OUT TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION ...

Page 12

... Min. — — — — (2) (3) — (1) — (1) — )". IL – t (actual WDD WP DDD 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES (6) IDT7024X17 IDT7024X20 IDT7024X25 Com'l Only Min. Max. Min. Max. Min. — 17 — 20 — — 17 — 20 — — 17 — 20 — — 17 — 17 — ...

Page 13

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins for the reading port. IL BUSY (slave input ...

Page 14

... IDT7024X35 Min — — 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES (1) TIMING ( BDC t BDA (1) IDT7024X20 IDT7024X25 Max. Min. Max. Min. — 0 — 0 — 0 — — 20 — 15 — 20 — IDT7024X55 IDT7024X70 Mil. Only Max. Min. Max. Min. — ...

Page 15

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM WAVEFORM OF INTERRUPT TIMING ADDR "A" "A" "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...

Page 16

... Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024. 2. There are eight semaphore flags written to via I/O FUNCTIONAL DESCRIPTION The IDT7024 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory ...

Page 17

... HIGH-SPEED DUAL-PORT STATIC RAM BUSY L Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs. applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation ...

Page 18

... The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7024 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the ...

Page 19

... USING SEMAPHORES—SOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT7024’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port ...

Page 20

... IDT7024S/L HIGH-SPEED DUAL-PORT STATIC RAM ORDERING INFORMATION IDT XXXXX A 999 Device Power Speed Type A A Package Process/ Temperature Range Blank 7024 6.15 MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial ( +70 C) Military (– +125 C) Compliant to MIL-STD-883, Class B 100-pin TQFP (PN100-1) 84-pin PGA (G84-3) ...

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