IDT72265 Integrated Device Technology, Inc., IDT72265 Datasheet
IDT72265
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IDT72265 Summary of contents
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... Integrated Device Technology, Inc. FEATURES: • 8,192 x 18-bit storage capacity (IDT72255) • 16,384 x 18-bit storage capacity (IDT72265) • 10ns read/write cycle time (8ns access time) • Retransmit Capability • Auto power down reduces power consumption • Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings • ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 automatically on the outputs, no read operation required. The state of the FWFT/SI pin during Master Reset determines the mode in use. The IDT72255/72265 FIFOs have five flag functions, OR (Empty Flag ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 gramming offset registers may not be convenient. The Retransmit function allows the read pointer to be reset to the first location in the RAM array synchronized to RT RCLK when ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read ...
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... Input High Voltage 2.0 — Commercial Input High Voltage 2.2 — Military Input Low Voltage — — Commercial & Military 10 – +125 C) A IDT72255L IDT72265L Military t = 15, 25ns CLK Typ. Max. Min. Typ. Max. — 1 –10 — 10 — 10 –10 — ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Military Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MRS MRS MASTER RESET ( ) A Master Reset is accomplished whenever the Master ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 When goes LOW, Retransmit Setup is complete; at the same time, the contents of the first location are automatically displayed on the outputs. Since FWFT Mode is selected, the first word ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 SEN SEN SERIAL ENABLE ( ) SEN Serial Enable enable used only for serial programming of the offset registers. The serial programming method must be selected during ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A ...
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... When FF is HIGH, the FIFO is not full reads are performed after a reset (either MRS or PRS), FF will go LOW after 8,192 writes tor the IDT72255 and 16,384 writes to the IDT72265. In FWFT Mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data ...
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... IDT72255, and (16,384-m) writes to the IDT72265. PAF ) will go LOW In FWFT Mode reads are performed after reset ( PRS or ), IDT72255, and (16,385-m) writes to the IDT72265. In this LD , case, the first word written to an empty FIFO does not stay memory, but goes unrequested to the output register; there- ...
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... In IDT Standard Mode reads are performed after reset MRS PRS ( or is the maximum FIFO depth (8,192 words for the IDT72255, 16,384 words for the IDT72265). In FWFT Mode reads are performed after reset ( MRS PRS 72265. In this case, the first word written to an empty FIFO does not stay in memory, but goes unrequested to the output register ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 MRS REN WEN t FWFT FWFT/SI LD (1) RT SEN PAE PAF MILITARY AND COMMERCIAL TEMPERATURE RANGES t RS ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 PRS REN WEN RT SEN PAE PAF MILITARY AND COMMERCIAL TEMPERATURE RANGES RSS t t ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 CLK t CLKH 1 WCLK WEN FF (1) t SKEW1 RCLK REN NOTES the minimum time between a rising RCLK edge and a ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 RCLK t t ENS ENH REN WCLK WEN NOTES contributes a variable delay to the overall first word ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 WCLK first valid write t ENS WEN (1) t FWL1 RCLK EF REN NOTES max. ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN OE LOW DATA IN OUTPUT ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 WCLK t DS DATA WRITE ENH ENS WEN (1) t FWL1 RCLK EF REN OE LOW DATA IN OUTPUT REGISTER ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 WCLK t ENS SEN t LDS BIT 0 Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes) NOTE: 1. For the 72255 ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 RCLK LD REN DATA IN OUTPUT REGISTER Q0 - Q17 Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes) NOTE =LOW t t CLKL CLKH WCLK ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 CLKL CLKH WCLK t t ENS ENH WEN PAF D - (m+1) Words in FIFO Memory RCLK REN NOTES: PAF 1. offset = 8,192 for IDT 72255, ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 WCLK ENS ENH RTS WEN RCLK t t ENS ENH t RTS REN ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES 25 ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES 26 ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 WCLK ENS ENH RTS WEN RCLK t t ENS t ENH RTS REN ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72255/72265 may be used when the applica- WRITE CLOCK (WCLK) WRITE ENABLE ( DATA IN (D SERIAL ENABLE( FIRST WORD FALL THROUGH/SERIAL INPUT FULL FLAG/INPUT ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 PRS PARTIAL RESET ( ) MRS MASTER RESET ( ) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RT RETRANSMIT ( ) DATA IN (Dn) 36 WRITE CLOCK (WCLK) WRITE ENABLE ( FULL ...
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IDT72255/72265 SyncFIFO 8,192 x 18, 16,384 x 18 where T is the RCLK period and T RCLK the WCLK period, whichever is shorter. The maximum amount of time it takes for a word to pass from the inputs of the ...