IDT72V821 Integrated Device Technology, Inc., IDT72V821 Datasheet
IDT72V821
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IDT72V821 Summary of contents
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... The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 WENA /LDA 2 WCLKA WENA 1 RSA COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following Symbol Name I Data Inputs Data Inputs RSA, ...
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... Ind’l) 2.0 — Input Low Voltage (Com’l & Ind’l) — — Operating Temperature 0 — Commercial Operating Temperature -40 Industrial IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 IDT72V851 Commercial and Industrial ( 10, 15 CLK Typ. Max. — –1 — 10 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 1 5 Com’l & Ind’l Commercial IDT72V801L15 IDT72V801L20 IDT72V811L15 IDT72V811L20 IDT72V821L15 IDT72V821L20 IDT72V831L15 IDT72V831L20 IDT72V841L15 IDT72V841L20 IDT72V851L15 IDT72V851L20 Min. Max. Min. 100 — 66.7 — 6 (1) — 15 — ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses. Data In (D ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values. If FIFO A (B) is ...
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... Array A (B) is full reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512 writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B) ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFA, PAFA ( NOTES: 1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ( OEA (OEB) WCLKA, WCLKB WENA1 (WENB1) WENA2 (WENB2) NOTE: is the minimum time between a rising WCLKA (WCLKB) ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 NO WRITE WCLKA (WCLKB) t SKEW1 ( FFA (FFB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) t ENH t ENS RENA1 (RENB2) OEA LOW (OEB ...
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... NOTES PAF offset. 2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841, or (8,192-m) words for the IDT72V851. is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between 3 ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 t CLK t CLKH WCLKA (WCLKB) LDA (LDB) WENA1 (WENB1 ( PAE OFFSET (LSB) t CLK t CLKH RCLKA (RCLKB) t LDA (LDB) t RENA1, RENA2 (RENB1, RENB2) QA ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 SINGLE DEVICE CONFIGURATION — When FIFO A ( Single Device Configuration, the Read Enable 2 RENA2 (RENB2) control input can WCLKA (WCLKB) WENA1 (WENB1) WENA2/LDA (WENB2/LDB Figure 14. Block Diagram of One ...
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IDT72V801/72V811/72V821/72V831/72V841/72V851 The two FIFOs contained in the IDT72V801/72V811/72V821/72V831/ 72V841/72V851 can be used to prioritize two different types of data shared on a system bus. When writing from the bus to the FIFO, control logic sorts Processor Clock Address Control Data ...
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... CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. The IDT72V801/72V811/72V821/72V831/72V841/72V851 operates in the Depth Expansion configuration when the following conditions are met: 1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables ...