ADSP-2189M Analog Devices, ADSP-2189M Datasheet
ADSP-2189M
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ADSP-2189M Summary of contents
Page 1
... RAM and 48K words (16-bit) of data RAM. Power-down circuitry is also pro- vided to meet the low power needs of battery operated portable equipment. The ADSP-2189M is available in a 100-lead LQFP package. In addition, the ADSP-2189M supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— ...
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... ADSP-2100 BASE ARCHITECTURE ® Figure 1. Functional Block Diagram Figure overall block diagram of the ADSP-2189M. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations. The ALU per- forms a standard set of arithmetic and logic operations ...
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... The ADSP-2189M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2189M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual, Third Edition. • SPORTs are bidirectional and have a separate, double-buff- ered transmit and receive section. • ...
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... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2189M processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...
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... The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2189M will remain in the idle state for maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. ...
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... IAD15-0 Figure 2. ADSP-2189M Basic System Interface Clock Signals The ADSP-2189M can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...
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... MODES OF OPERATION Setting Memory Mode Memory Mode selection for the ADSP-2189M is made during chip reset through the use of the Mode C pin. This pin is multi- plexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive ...
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... ADSP-2189M. Program Memory Program Memory, Full Memory Mode is a 24-bit-wide space for storing both instruction op codes and data. The ADSP-2189M has 32K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. ...
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... DM(0x3FFE) The ADSP-2189M has a programmable memory select signal that is useful for generating memory select signals for memories IOWAIT0 mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality ...
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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2189M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...
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... DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) di- rects the ADSP-2189M to write the address onto the IAD0-14 bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register ...
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... DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-2189M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2189M is performing an external memory access ...
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... The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2189M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. ...
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... Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... V 2 CLKOUT 3.3 V Total power dissipation for this example is P Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2189M. The curves represent the current drive capability of the output drivers as a function of output voltage Symbol Value –20 θ ...
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... MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM DD INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO ADSP-2189M STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND. Figure 15. Power vs. Frequency REV. A CAPACITIVE LOADING ...
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... ADSP-2189M TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The out- put disable time ( the difference of t DIS as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 ...
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... Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT * PF(3:0) RESET REV. A Min 26 0.5t – 0.5t – CKI t CKIH t CKIL t CKOH t CKH t CKL PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A Figure 22. Clock Signals –19– ADSP-2189M Max Unit ...
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... ADSP-2189M Parameter Interrupts and Flags Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low t IFS IRQx, FI, or PFx Hold after CLKOUT High t IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...
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... BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. CLKOUT BR CLKOUT PMS, DMS BMS BGH REV SDB t SDBH Figure 24. Bus Request–Bus Grant –21– ADSP-2189M Min Max 0.25t + 2 CK 0.25t + 10 CK 0.25t + 0.25t – SEC SEH Unit ...
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... ADSP-2189M Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted t RDA ...
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... A0–A13 DMS, PMS, BMS, CMS, IOMS REV. A Min 0.5t 0.25t 0.5t 0 0.25t 0.25t 0.25t 0.75t 0.25t 0.5t t WRA WWR ASW CWR WDE Figure 26. Memory Write –23– ADSP-2189M Max Unit – – – – – – 2 0.25t + – – – DDR ...
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... ADSP-2189M Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLKIN Width SCP Switching Characteristics: t CLKOUT High to SCLKOUT CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...
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... End of Address Latch = IS High or IAL Low Start of Write or Read = IS Low and IWR Low or IRD Low. IACK IAL IS IAD15– REV IKA t IALD t t IALP IALP t t IASU IASU t IAH Figure 28. IDMA Address Latch –25– ADSP-2189M Min Max IAH t IALS Unit ...
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... ADSP-2189M Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW t Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristics: Start of Write to IACK High t IKHW ...
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... This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition. IACK IS IWR IAD15–0 REV IDSU IDH , t . IKSU IKH t IKW t IKHW t IKLW t IKSU DATA Figure 30. IDMA Write, Long Write Cycle –27– ADSP-2189M Min Max IKH Unit ...
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... ADSP-2189M Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR End of Read after IACK Low t IRK Switching Characteristics: IACK High after Start of Read t IKHR IAD15–0 Data Setup before IACK Low t IKDS t IAD15–0 Data Hold after End of Read ...
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... IAD15–0 Previous Data Valid after Start of Read IRDV NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. REV IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD15–0 DATA t IRDV Figure 32. IDMA Read, Short Read Cycle –29– ADSP-2189M Min Max IKDH t IKDD Unit ...
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... A11/IAD10 A12/IAD11 10 11 A13/IAD12 12 GND 13 CLKIN 14 XTAL V 15 DDEXT 16 CLKOUT GND DDINT BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead LQFP Package Pinout ADSP-2189M TOP VIEW (Not to Scale) –30– 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 DDEXT 66 GND D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 ...
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... The ADSP-2189M package pinout appears in the following table. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...
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... Part Number Ambient Temperature Range ADSP-2189MKST-300 0°C to +70°C ADSP-2189MBST-266 –40°C to +85°C *In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages (1.6 mm thick) are now designated as LQFP. OUTLINE DIMENSIONS Dimensions shown in inches and (mm) ...