IDT72V271 Integrated Device Technology, Inc., IDT72V271 Datasheet
IDT72V271
Available stocks
Related parts for IDT72V271
IDT72V271 Summary of contents
Page 1
... The IDT72V261LA/72V271LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and INPUT REGISTER RAM ARRAY 16,384 x 9 32,768 x 9 OUTPUT REGISTER IDT72V261LA IDT72V271LA LD SEN OFFSET REGISTER FF/IR PAF EF/OR FLAG PAE LOGIC HF FWFT/SI READ POINTER READ RT CONTROL LOGIC RCLK ...
Page 2
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock input with ...
Page 3
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, ...
Page 4
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock ...
Page 5
... Input High Voltage (Com’l/Ind’l) 2.0 Input Low Voltage (Com’l/Ind’l) Operating Temperature 0 Commercial Operating Temperature 0 Industrial IDT72V261LA IDT72V271LA Commercial & Industrial ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
Page 6
... GND to 3.0V 3ns 1.5V 1.5V * Includes jig and scope capacitances. See Figure 1 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l (2) Commercial IDT72V261LA15 IDT72V261LA20 IDT72V271LA15 IDT72V271LA20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — ...
Page 7
... LOW. Again reads are performed, the PAF will go LOW after (16,384-m) writes for the IDT72V261LA and (32,768-m) writes for the IDT72V271LA. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. This parameter is also user programmable ...
Page 8
... Master Reset, regardless of whether serial or parallel programming has been selected 16,384 16,385 to (32,768-(m+1)) (2) to 16,383 (32,768- 16,385 (2) 16,386 to (32,769-(m+1)) (32,769-m) 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FF PAF IDT72V261LA ( (2) to 32,767 H L 32,768 PAF IDT72V271LA ( n ( (2) to 32,768 L L 32,769 PAE ...
Page 9
... The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 4. Programmable Flag Offset Programming Sequence IDT72V271LA 32,768 x 9 − BIT ...
Page 10
... SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 28 bits for the IDT72V261LA and 30 bits for the IDT72V271LA. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
Page 11
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 When EF goes HIGH, Retransmit setup is complete and read opera- tions may begin starting with the first location in memory. Since IDT Standard mode is selected, ...
Page 12
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever ...
Page 13
... When FF is HIGH, the FIFO is not full reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO (D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information. SKEW In FWFT mode, the Input Ready (IR) function is selected ...
Page 14
... In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA. In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO, where D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA ...
Page 15
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS RSR t t ...
Page 16
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT ...
Page 17
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN ...
Page 18
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
Page 19
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...
Page 20
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t ENH t ENS t RTS REN WCLK WEN t ENS RT EF PAE HF PAF 1 ...
Page 21
... FIFO after Master Reset goes LOW RCLK cycles + t . REF WCLK t ENS SEN t LDS BIT 0 NOTE for the IDT72V261LA and for the IDT72V271LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF PAF Figure 12. Retransmit Timing (FWFT Mode) t ...
Page 22
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading ...
Page 23
... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA. 2. For FWFT mode maximum FIFO depth 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
Page 24
IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any ...
Page 25
... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V261LA can easily be adapted to applications requiring depths greater than 16,384 and 32,768 for the IDT72V271LA with a 9- bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
Page 26
ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. DATASHEET DOCUMENT HISTORY 04/25/2001 pgs. ...
Page 27
... Not Given WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching ™ IDT72V261LA IDT72V271LA Comments In the LA part this pin must be tied to either V or GND and must CC not toggle after reset. ( (ns) First word latency in the LA part is RCLK a fixed value, independent of the frequency of RCLK or WCLK ...