HDMP-0482 Hewlett-Packard, HDMP-0482 Datasheet
HDMP-0482
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HDMP-0482 Summary of contents
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... Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capabil- ity included. This device mini- mizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk ...
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... FM_NODE[0]_DV MODE_VDD BYPASS0 Figure 1. Block Diagram of HDMP-0482. HDMP-0482 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking ...
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... Buffered Line Logic (BLL) circuit that has on-chip source termination external bias resistors are required. The BLL Outputs on the HDMP-0482 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, ...
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... FM_NODE[0]_DV BYPASS0 Figure 2. Block Diagram of HDMP-0482, MODE_VDD is HIGH FM_NODE[0]_DV Figure 3. Block Diagram of HDMP-0482, MODE_VDD is LOW CDR CDR ...
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... FM_NODE[7]_AV 14 FM_NODE[0]- 15 FM_NODE[0 Figure 4. HDMP-0482 Package Layout and Marking, Top View. nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision Supplier Code; YYWW = Date Code (YY = year work week); COUNTRY = country of manufacture (on back side). Table 2. I/O Type Definitions. I/O Type Definition I-LVTTL LVTTL Input ...
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... Table 3. Pin Definitions for HDMP-0482. Pin Name Pin Pin Type TO_NODE[0]+ 20 HS_OUT TO_NODE[0]- 19 TO_NODE[1]+ 23 TO_NODE[1]- 22 TO_NODE[2]+ 32 TO_NODE[2]- 31 TO_NODE[3]+ 35 TO_NODE[3]- 34 TO_NODE[4]+ 44 TO_NODE[4]- 43 TO_NODE[5]+ 47 TO_NODE[5]- 46 TO_NODE[6]+ 57 TO_NODE[6]- 56 TO_NODE[7]+ 60 TO_NODE[7]- 59 FM_NODE[0]+ 16 HS_IN FM_NODE[0]- 15 FM_NODE[1]+ 26 FM_NODE[1]- 25 FM_NODE[2]+ 29 FM_NODE[2]- 28 FM_NODE[3]+ 38 FM_NODE[3]- 37 FM_NODE[4]+ 41 FM_NODE[4]- 40 FM_NODE[5]+ 51 FM_NODE[5]- 50 FM_NODE[6]+ ...
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... Table 3, continued. Pin Definitions for HDMP-0482. Pin Name Pin Pin Type GND VCCA 8 S VCCHS[0, VCCHS[2, VCCHS[ VCCHS[ VCCHS[6, VCC HDMP-0482 Absolute Maximum Ratings T =25° C, except as specified. Operation in excess of any of these conditions may result in permanent a damage to this device. T refers to the ambient temperature for the board upon which the parametric a measurements were taken ...
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... OP,HS_OUT HDMP-0482 Power Dissipation 0°C to +70° Symbol Parameter P Power Dissipation D HDMP-0482 Output Jitter Characteristics, T Symbol Parameter RJ Random Jitter at TO_NODE pins (1 sigma rms) DJ Deterministic Jitter at TO_NODE pins (pk-pk) Please refer to Figures 6 and 7 for jitter measurement setup information. HDMP-0482 Locking Characteristics, T Parameter ...
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... Figure 7. Setup for Measurement of Deterministic Jitter. 9 HDMP-0482 BYPASS[0]- +/- FM_NODE[0] BYPASS[1:4]- REFCLK +/- TO_NODE[0] 1.4V 2 106.25 MHz Ch 1/2 HP 83480A Digital Trigger Communication Analyzer HDMP-0482 BYPASS[0]- +/- FM_NODE[0] BYPASS[1:4]- REFCLK +/- TO_NODE[0] 1.4V 2 106.25 MHz Ch 1/2 HP 83480A Digital Trigger Communication 53.125 MHz Analyzer N/C 1 KΩ ...
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O-LVTTL Vcc ESD Protection GND Figure 8. O_LVTTL and I_LVTTL Simplified Circuit Schematic. HS_OUT 75 Ohms TO_NODE[n]+ TO_NODE[n]- GND ESD Protection Figure 9. HS_OUT and HS_IN Simplified Circuit Schematic. Note: FM_NODE[n] inputs should never be connected to ground as permanent ...
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... HDMP-0482 14.00 ±0.10 Tolerance 11 = 0°C to 85° 3.15V to 3.45V C CC Unit Typ. Max. °C/W 9.5 — for these devices is 39.4°C/W for the HDMP-0482 (θ where the power being D Details Plastic 85% Tin, 15% Lead 300 – 800 micro-inches 0.20 mm max. ...
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... India, Australia, New Zealand: (65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (65) 6755 2044 Taiwan: (65) 6755 1843 Data subject to change. Copyright © 2003 Agilent Technologies, Inc. Obsoletes 5988-7140EN June 16, 2003 5988-9758EN HDMP-0482 VCC VCC ...