PDI1394P11ABD Philips Semiconductors, PDI1394P11ABD Datasheet
PDI1394P11ABD
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PDI1394P11ABD Summary of contents
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PDI1394P11A 3-port physical layer interface Preliminary specification Philips Semiconductors INTEGRATED CIRCUITS 1999 Mar 10 ...
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... D3 16 1999 Mar 10 2.0 DESCRIPTION The Philips Semiconductors PDI1394P11A is an IEEE1394-1995 compliant Physical Layer interface. The PDI1394P11A provides the analog physical layer functions needed to implement a three port node in a cable-based IEEE 1394–1995 network. Additionally, the device manages bus initialization and arbitration cycles, as well as transmission and reception of data bits ...
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... Philips Semiconductors 3-port physical layer interface 5.0 PIN DESCRIPTION PIN NUMBER PIN SYMBOL 1 RESET– 2 LPS 3 LREQ 4 DVDD 5, 6, 19, 20 DVDDD 10, 17, 18, 63, 64 DGND 9 SYSCLK 11, 12 CTL[0:1] 13, 14, 15, 16 D[0:3] 22, 21 TESTM[1:2] 23 CPS 24, 25, 51, 55 AVDD 26, 32, 41, 49, 50, 61 AGND 27 C/LKON ...
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... Philips Semiconductors 3-port physical layer interface 6.0 BLOCK DIAGRAM CPS LPS ISO– CNA SYSCLK LREQ LINK INTERFACE CTL0 CTL1 PC0 PC1 PC2 C/LKON TESTM1 TESTM2 RESET– PD 7.0 FUNCTIONAL SPECIFICATION The PDI1394P11A is an IEEE1394–1995 High Performance Serial Bus Specification compliant physical layer interface device. It provides an interface between an attached link layer controller and three 1394 cable interface ports ...
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... Philips Semiconductors 3-port physical layer interface associated link controller. The received data is also transmitted out the other active cable ports. The cable status, bus initialization and arbitration states are monitored through the cable interface using differential comparators. The outputs of these comparators are used by internal logic to determine cable and arbitration status ...
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... Philips Semiconductors 3-port physical layer interface 9.0 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL SYMBOL PARAMETER PARAMETER V DC supply voltage input voltage input voltage I, output voltage input diode current output diode current ...
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... Philips Semiconductors 3-port physical layer interface 12.0 OTHER DEVICE I/O SYMBOL SYMBOL PARAMETER PARAMETER Supply current ly current Cable Power Threshold Voltage P V High-level output voltage OH V Low-level output voltage OL Input current, LREQ, LPS, PD TESTM[1:2] OFF-state output current, CTLn Dn, C/LKON I/Os, PC[0:2] inputs ...
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... Philips Semiconductors 3-port physical layer interface 14.0 AC SWITCHING CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER Transmit jitter Transmit skew t Transmit rise time r t Transmit fall time f Dn, CTLn, LREQ input setup time SYSCLK Dn, CTLn, LREQ input hold time t H from SYSCLK t Delay time, SYSCLK to Dn, CTLn D 15 ...
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... Philips Semiconductors 3-port physical layer interface 16.0 INTERNAL REGISTER CONFIGURATION The accessible internal registers of this device are listed in the following tables: ADDRESS 0 1 0000 0001 RHB IBR 0010 SPD 0011 AStat1 0100 AStat2 0101 AStat3 0110 Loopint CPSint 0111 Reserved 1000 ...
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... Philips Semiconductors 3-port physical layer interface 17.0 APPLICATION INFORMATION 49 50 VDD 0 12pF 6. 12pF 61 ISO– PDI1394P11 CABLE PORT Figure 4. Twisted pair cable interface connections 1999 Mar 10 TP CABLES TPBIAS TP CABLES AGND AGND AVDD PLLGND PLLGND FILTER AVDD XI PDI1394P11A XO PLLVDD R0 R1 AGND ISO– ...
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... Philips Semiconductors 3-port physical layer interface 17.1 Arbitrated (short) Bus Reset A 1394-1995 software initiated bus reset assumes that the state of the bus is unknown when reset occurs and requires that the reset be long enough to permit the longest transaction to finish and still complete reset (167 s min. to 250 s max.). The total duration of bus initialization is longer than the nominal isochronous cycle time (125 s) and may disrupt two isochronous periods ...
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... Philips Semiconductors 3-port physical layer interface 17.3 Bushold and Link/PHY single capacitor galvanic isolation 17.3.1 Bushold The PDI1394P11A uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. ...
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... Philips Semiconductors 3-port physical layer interface 18.0 EXTERNAL COMPONENTS AND CONNECTIONS 18.1 Logic Reset input (RESET–, pin 1) Forcing this pin low causes a Bus Reset condition on the active cable ports, and resets the internal logic to the Reset Start state. SYSCLK remains active. For power up (and after power down is asserted delay is required to assure proper PLL operation ...
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... Philips Semiconductors 3-port physical layer interface 18.17 Current setting resistor (R[0:1], pins [59,60]) An internal reference voltage is applied across the resistor connected between these two pins to set the internal operating and the cable driver output currents. A low TCR (<150ppm/ C temperature coefficient) with a value of 6. meet the 1394 standard output voltage limits. 18.18 Isolation Barrier disable (ISO– ...
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... Philips Semiconductors 3-port physical layer interface 19.2.4 Other Requests and LREQ The three bit Request Type field has the following possible values: BIT(S) NAME DESCRIPTION 000 ImmReq Immediate request: Upon detection of an idle, take control of the bus immediately (no arbitration) 001 IsoReq ...
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... Philips Semiconductors 3-port physical layer interface 20.0 STATUS REQUEST, LENGTH OF STREAM: 16 BITS BIT(S) NAME DESCRIPTION 0 Arbitration reset gap Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is defined in the P1394 standard). This bit is used by the link in its busy/retry state machine. ...
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... Philips Semiconductors 3-port physical layer interface 22.0 TRANSMIT When the link wants to transmit information, it will first request access to the bus through the LREQ pin. Once the phy receives this request, it will arbitrate to gain control of the bus. When the phy wins ownership of the serial bus, it will grant the bus to the link by asserting the ‘ ...
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... Philips Semiconductors 3-port physical layer interface 23.0 RECEIVE When data is received by the phy from the serial bus, it will transfer the data to the link for further processing. The phy will assert ‘Receive’ on the CTL lines and ‘1’ on each D pin. The phy indicates the start of the packet by placing the speed code on the data bus. The phy will then proceed with the transmittal of the packet to the link on the D lines while still keeping the ‘ ...
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... Philips Semiconductors 3-port physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 1999 Mar 10 PDI1394P11A 19 Preliminary specification SOT314-2 ...
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... Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no ...