SN54LS166J Freescale Semiconductor, Inc, SN54LS166J Datasheet

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SN54LS166J

Manufacturer Part Number
SN54LS166J
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8-BIT SHIFT REGISTERS
buffered, the drive requirements are lowered to one 54/ 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode.
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command with
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
The LS166 is a parallel-in or serial-in, serial-out shift register and has a
Synchronous Load
Direct Overriding Clear
Parallel to Serial Conversion
SERIAL
INPUT
V CC
16
1
CLEAR
CLEAR
SHIFT/
LOAD
SHIFT/
LOAD
SERIAL INPUT
H
H
H
H
H
L
15
2
A
A
PARALLEL INPUTS
PARALLEL
INPUT OUTPUT
14
H
B
3
H
B
SHIFT/
SHIFT/
LOAD
LOAD
X
X
H
H
X
L
Q H
13
Q H
C
4
C
CLOCK
CLOCK
INHIBIT
INHIBIT
PARALLEL INPUTS
12
G
G
5
D CLOCK
D
X
H
L
L
L
L
INHIBIT
INHIBIT
CLOCK
11
F
6
F
INPUTS
CLOCK
CLOCK
CLEAR
CLOCK GND
10
CK
FAST AND LS TTL DATA
E
X
7
L
E
CLEAR
FUNCTION TABLE
9
8
SERIAL
SERIAL
X
X
X
H
X
L
5-1
PARALLEL
A . . . H
a . . . h
X
X
X
X
X
Q A0
Q A0
Q A
H
INTERNAL
INTERNAL
L
a
L
OUTPUTS
OUTPUTS
16
16
SN54/74LS166
8-BIT SHIFT REGISTERS
ORDERING INFORMATION
16
LOW POWER SCHOTTKY
1
1
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Q B0
Q An
Q An
Q B0
Q B
b
L
1
OUTPUT
OUTPUT
Q H0
Q Gn
Q Gn
Q H0
Q H
Q H
L
h
Ceramic
Plastic
SOIC
CASE 751B-03
CASE 620-09
CASE 648-08
CERAMIC
N SUFFIX
D SUFFIX
J SUFFIX
PLASTIC
SOIC

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SN54LS166J Summary of contents

Page 1

SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. ...

Page 2

Typical Clear, Shift, Load, Inhibit, and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD PARALLEL INPUTS OUTPUT Q H CLEAR SERIAL INPUT SHIFT/LOAD CLOCK INHIBIT SN54/74LS166 ...

Page 3

GUARANTEED OPERATING RANGES Symbol Parameter V CC Supply Voltage T A Operating Ambient Temperature Range I OH Output Current — High I OL Output Current — Low DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Symbol Symbol Parameter Parameter V IH Input ...

Page 4

TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT FOR TEST Serial Input t w(clear) CLEAR INPUT V ref V ref CLOCK INPUT t w(clock) DATA INPUT (SEE TEST TABLE) t PHL (clear-Q) OUTPUT Q AC CHARACTERISTICS ( ...

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