GX1-300B-85-2.0 National Semiconductor, GX1-300B-85-2.0 Datasheet

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GX1-300B-85-2.0

Manufacturer Part Number
GX1-300B-85-2.0
Description
Processor, Low Power Integrated Solution Processor
Manufacturer
National Semiconductor
Datasheet

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© 2002 National Semiconductor Corporation
Geode™ GX1 Processor Series
Low Power Integrated x86 Solution
General Description
The National Semiconductor
series is a line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
sumers and business professionals alike, it’s the perfect
solution for IA (information appliance) applications such as
thin clients, interactive set-top boxes, and personal internet
access devices.
Geode™ GX1 Processor Internal Block Diagram
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, WebPAD, and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
SYSCLK
SUSPA#
SUSP#
REQ/GNT
Management
Arbiter
Pairs
Clock Module
multiplied
Control
SYSCLK
3
Power
by “A”
Unified L1
Cache
Controller
16 KB
PCI Host
Bus
PCI
X-Bus (32)
C-Bus (64)
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
®
Core
Clocks
X-Bus
Clocks
(128)
Geode™ GX1 processor
2D Accelerator
BLT Engine
ROP Unit
VGA
Instruction
Fetch
TLB
x86 Compatible Core
Arbiter
SDRAM
Clocks
Load/Store
The Geode GX1 processor series is divided into three main
categories as defined by the core operating voltage. Avail-
able with core voltages of 2.2V, 2.0V, and 1.8V, it offers
extremely low typical power consumption (1.4W, 1.2W,
and 0.8W, respectively) leading to longer battery life and
enabling small form-factor, fanless designs. Typical power
consumption is defined as an average, measured running
Microsoft Windows at 80% Active Idle (Suspend-on-Halt)
with a display resolution of 800x600x8 bpp at 75 Hz.
4
divide by “B”
X-Bus CLK
Integer
MMU
Unit
Controller
X-Bus
SDRAM
64-bit
Buffers
Write
INT/NMI
Companion Interface
Compression Buffer
RGB
Display Controller
Geode™ Graphics
Timing Generator
Palette RAM
Floating Point
FP_Error
Unit
Interrupt
Control
Read
Buffers
YUV
www.national.com
INTR
IRQ13
SMI#
June 2002

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GX1-300B-85-2.0 Summary of contents

Page 1

... Geode, WebPAD, and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2002 National Semiconductor Corporation The Geode GX1 processor series is divided into three main categories as defined by the core operating voltage. Avail- able with core voltages of 2.2V, 2.0V, and 1.8V, it offers extremely low typical power consumption (1 ...

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... Internet content available, the intelligent integration of several other functions, such as audio and graphics, offers a true system-level multimedia solution. The Geode GX1 processor core is a proven x86 design that offers competitive performance. It contains integer and floating point execution units based on sixth-generation technology ...

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Flexible Power Management Supports a wide variety of standards:  — APM (Advanced Power Management) for Legacy power management — ACPI (Advanced Configuration and Power Interface) for Windows power management – Direct support for all standard processor (C0-C4) states — ...

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... INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6 INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6.1 Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6.2 Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6.3 XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6.4 PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.7 GEODE GX1/CS5530A SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.7.1 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 PCI Interface Signals ...

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Table of Contents (Continued) 3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ...

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Table of Contents (Continued) 4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... VGA Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 VGA Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 GX1 VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VGA Range Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VGA Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VGA Write/Read Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VGA Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VGA Memory ...

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... Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.1.3 CPU Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.1.3.1 5.1.3.2 5.1.4 3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.1.5 GX1 Processor Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.1.6 Advanced Power Management (APM) Support . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.2 SUSPEND MODES AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.2.1 Timing Diagram for Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.2.2 Initiating Suspend with SUSP 180 5 ...

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Table of Contents (Continued) 7.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... MHz. These features are made possi- ble by the use of advanced-process technologies and pipe- lining. The GX1 processor has low power consumption at all clock frequencies. Where additional power savings are required, designers can make use of Suspend Mode, Stop Clock capability, and System Management Mode (SMM) ...

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... The 16 KB write-back unified (data/instruction) cache is configured as four-way set associative. The cache stores code and data in 1024 cache lines. The GX1 processor provides the ability to allocate a portion of the L1 cache as a scratchpad, which is used to acceler- ate the Virtual Systems Architecture technology algorithms as well as for some graphics operations ...

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... The internal bus interface unit contains address mapping logic that determines if memory accesses are tar- geted for the SDRAM or for the PCI bus. The PCI bus in a GX1 based system is 3.3 volt only. Do not connect 5 volt devices on this bus. 12 Revision 4.1 ...

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... DSTN flat panel LCD. It can drive all standard color DSTN flat panels 1024x768 resolution. Figures 1-4 and 1-5 show the signal connections between the GX1 processor and the CS5530A. For connections to the CS9211, refer to the CS9211 data book. SDRAM Port Geode™ ...

Page 14

... Geode™ GX1 Processor Nonexclusive Interconnect Signals (May also connect to other 3.3V circuitry) Note: Refer to Figure 1-5 for interconnection of the pixel lines. Figure 1-4. Geode™ GX1/CS5530A Signal Connections www.national.com Pixel Port 18 Geode™ Timing Control 4 CS9211 Graphics Serial Configuration ...

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... Architecture Overview (Continued) Geode™ GX1 R Processor G B Revision 4.1 PIXEL17 PIXEL23 PIXEL16 PIXEL22 PIXEL15 PIXEL21 PIXEL14 PIXEL20 PIXEL13 PIXEL19 PIXEL12 PIXEL18 PIXEL17 PIXEL16 PIXEL11 PIXEL15 PIXEL10 PIXEL14 PIXEL9 PIXEL13 PIXEL8 PIXEL12 PIXEL7 PIXEL11 PIXEL6 PIXEL10 PIXEL9 PIXEL8 PIXEL5 PIXEL7 PIXEL4 ...

Page 16

... Architecture Overview (Continued) 1.7.1 Reference Designs As described previously, the GX1 series of integrated pro- cessors is designed specifically to work with National’s Geode I/O and graphics companion devices. To help define and drive the emerging information appliance market, sev- eral reference systems have been developed by National Semiconductor ...

Page 17

... Architecture Overview (Continued) SDRAM SO-DIMM Geode™ Video GX1 3.3V PCI Bus Processor NSC DP83815 Ethernet Controller Reset CPU Core PWR CTL Power Figure 1-7. Example Thin Client System Diagram Revision 4.1 Geode™ CS5530A I/O Companion ISA Bus Termination Clock ...

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... Hard Drive Notebook Notebook DVD Floppy Drive Drive Internal Assembly Options TDA8006 Smartcard Figure 1-8. Example Set-Top Box System Diagram www.national.com NSC Geode™ GX1 DMA Processor Arbiter 3.3V PCI Bus C-CUBE SDRAM “ZIVA” Geode™ CS5530A Optional I/O V.90 ...

Page 19

... Signal Definitions This section describes the external interface of the Geode GX1 processor. Figure 2-1 shows the signals organized by their functional interface groups (internal test and electrical pins are not shown). SYSCLK CLKMODE[2:0] RESET System INTR IRQ13 Interface SMI# Signals SUSP# ...

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Signal Definitions (Continued) 2.1 PIN ASSIGNMENTS The tables in this section use several common abbrevia- tions. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the 352 BGA with Table 2-2 and Table 2-3 ...

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... V CC3 CC2 STOP# SERR# CBE1# AD13 AD10 AD8 V CC3 CC2 CC3 CC2 Geode™ GX1 Processor 352 BGA - Top View CC3 CC2 MD59 MD26 MD56 MD55 MD22 CKEB V CC3 CC2 MD28 MD58 MD25 MD24 MD54 MD21 V CC3 CC2 MD60 MD27 MD57 ...

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Signal Definitions (Continued) Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number Pin Pin No. Signal Name No. Signal Name A1 V B23 MD1 B24 MD33 SS A3 AD27 B25 AD24 B26 ...

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Signal Definitions (Continued) Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued) Pin Pin No. Signal Name No. Signal Name AB1 DCLK AC16 V SS AB2 PIXEL17 AC17 V CC2 AB3 VID_DATA6 AC18 V SS AB4 VID_DATA7 ...

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Signal Definitions (Continued) Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name 1 Signal Name Type Pin No. Signal Name AD0 I/O A21 DQM0 AD1 I/O A22 DQM1 AD2 I/O A19 DQM2 AD3 I/O B19 DQM3 AD4 ...

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Signal Definitions (Continued) Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) 1 Signal Name Type Pin No. Signal Name V PWR K1 V CC2 CC3 V PWR K2 V CC2 CC3 V PWR K3 V ...

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... FRAME# V PAR V AD10 V SS CC3 SS AD17 IRDY# PERR# AD14 AD12 AD7 INTR V DEVSEL# AD15 V CBE0# AD5 SS SS Geode™ GX1 Processor 320 SPGA - Top View V MD60 MD57 V MD22 MD52 SS SS MD29 MD27 MD56 MD55 MD21 MD20 V MD58 V MD23 V SS CC3 SS MD30 ...

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Signal Definitions (Continued) Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number Pin Pin No. Signal Name No. Signal Name A3 V C25 AD4 CC3 A5 AD25 C27 AD0 A7 V C29 V SS CC2 A9 V C31 ...

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Signal Definitions (Continued) Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number (Continued) Pin Pin No. Signal Name No. Signal Name AJ27 V AK24 MD20 CC2 AJ29 V AK26 MD50 CC2 AJ31 V AK28 MD16 SS AJ33 BA1 ...

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Signal Definitions (Continued) Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name 1 Signal Name Type Pin. No. Signal Name AD0 I/O C27 DQM0 AD1 I/O B30 DQM1 AD2 I/O A27 DQM2 AD3 I/O B26 DQM3 AD4 ...

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Signal Definitions (Continued) Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) 1 Signal Name Type Pin. No. Signal Name V PWR A29 V CC2 CC2 V PWR C9 V CC2 CC2 V PWR C29 V ...

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... The SYSCLK to core clock multiplier is configured using the CLKMODE[2:0] inputs. The SYSCLK input is a fixed frequency which can only be stopped or varied when the GX1 processor is in full 3V Sus- pend. (See Section 5.1.4 "3 Volt Suspend" on page 178 for details regarding this mode.) ...

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... M4 I Suspend Request (PU) This signal is used to request that the GX1 processor enter Suspend mode. After recognition of an active SUSP# input, the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. SUSP# is enabled by setting the USE_SUSP bit in CCR2 (Index C2h[7]), and is ignored following RESET ...

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Signal Definitions (Continued) 2.2.2 PCI Interface Signals BGA Signal Name Pin No. FRAME# A8 (PU) IRDY# C9 (PU) TRDY# B9 (PU) STOP# C11 (PU) Revision 4.1 SPGA Pin No Type Description C13 s/t/s Frame (PU) FRAME# is driven by the ...

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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. AD[31:0] Refer to Table 2-3 C/BE[3:0]# D5, B8, C13, A15 PAR B12 www.national.com SPGA Pin No Type Description Refer to I/O Multiplexed Address and Data Table 2-5 ...

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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. LOCK# B11 (PU) DEVSEL# A9 (PU) PERR# A11 (PU) SERR# C12 (PU) REQ[2:0]# D3, H3, E3 (PU) Revision 4.1 SPGA Pin No Type Description B16 s/t/s Lock ...

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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. GNT[2:0]# E1, F2, D1 2.2.3 Memory Controller Interface Signals BGA Signal Name Pin No. MD[63:0] Refer to Table 2-3 MA[12:0] Refer to Table 2-3 BA[1:0] AD26, AD25 ...

Page 37

... AL7, based on these clocks. AK8 AK12 I SDRAM Clock Input The GX1 processor samples the memory read data on this clock. Works in conjunction with the SDCLK_OUT signal. AL13 O SDRAM Clock Output This output is routed back to SDCLK_IN. The board designer should vary the length of the board trace to control skew between SDCLK_IN and SDCLK ...

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Signal Definitions (Continued) 2.2.4 Video Interface Signals (Continued) BGA Signal Name Pin No FP_HSYNC L2 FP_VSYNC J1 ENA_DISP AD5 VID_RDY AD1 VID_VAL M2 VID_DATA[7:0] Refer to Table 2-3 PIXEL[17:0] Refer to Table 2-3 www.national.com SPGA Pin No Type Description R4 ...

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... AM36 SPGA Pin No. Type Description AJ3 I Float Float forces the GX1 processor to float all outputs in the high- impedance state and to enter a power-down state. AL11 O Raw Clock This output is the GX1 processor clock. This debug signal can be used to verify clock operation. D28, ...

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Signal Definitions (Continued) 2.2.6 Internal Test and Measurement Signals (Continued) BGA Signal Name Pin No. TEST F3 (PD) TDP D26 TDN E24 www.national.com SPGA Pin No. Type Description J5 I Test (PD) Test-mode input. This pin is internally connected to ...

Page 41

... Global Descriptor Table Register Revision 4.1 3.1 CORE PROCESSOR INITIALIZATION The GX1 processor is initialized when the RESET signal is asserted. The processor is placed in real mode and the registers listed in Table 3-1 are set to their initialized val- ues. RESET invalidates and disables the CPU cache, and turns off paging ...

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Processor Programming Table 3-1. Initialized Core Register Controls (Continued) Register Register Name LDTR Local Descriptor Table Register TR Task Register CR0 Control Register 0 CR2 Control Register 2 CR3 Control Register 3 CR4 Control Register 4 CCR1 Configuration Control 1 ...

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... Processor Programming 3.2 INSTRUCTION SET OVERVIEW The GX1 processor instruction set can be divided into nine types of operations: • Arithmetic • Bit Manipulation • Shift/Rotate • String Manipulation • Control Transfer • Data Transfer • Floating Point • High-Level Language Support • Operating System Support The GX1 processor instructions operate on as few as zero operands and as many as three operands ...

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... I/O access, string operations, stack operations, loop, variable shift and rotate, and translate instructions. The GX1 processor implements a stack using the ESP reg- ister. This stack is accessed during the PUSH and POP instructions, procedure calls, procedure returns, interrupts, exceptions, and interrupt/exception returns ...

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Processor Programming General Purpose Registers Segment (Selector) Registers Instruction Pointer and EFLAGS Registers Revision 4.1 (Continued) Table 3-2. ...

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Processor Programming 3.3.1.2 Segment Registers The 16-bit segment registers, part of the main memory addressing mechanism, are described in Section 3.5 "Off- set, Segment, and Paging Mechanisms" on page 66. The six segment registers are: CS- Code Segment DS- Data ...

Page 47

... Processor Programming 3.3.1.4 EFLAGS Register The EFLAGS register contains status information and con- trols certain operations on the GX1 processor. The lower Bit Name Flag Type 31:22 RSVD -- 21 ID System 20:19 RSVD -- 18 AC System 17 VM System 16 RF Debug 15 RSVD -- 14 NT System 13:12 ...

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... The Configuration Registers are used to define the GX1 CPU setup including cache management. The Debug Registers provide debugging facilities for the GX1 processor and enable the use of data access break- points and code execution breakpoints. The Test Registers provide a mechanism to test the con- tents of both the on-chip 16 KB cache and the Translation Lookaside Buffer (TLB) ...

Page 49

... This further reduces the number of DWORD write operations needed during a replacement or flush opera- tion. The GX1 processor will cache SMM regions, reducing sys- tem management overhead to allow for hardware emula- tion such as VGA. Table 3-6. Control Registers Map ...

Page 50

Processor Programming Table 3-7. CR4-CR0 Bit Definitions (Continued) Bit Name Description 11:0 RSVD Reserved: Set to 0. CR2 Register 31:0 PFLA Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the ...

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Processor Programming 3.3.2.2 Configuration Registers The Configuration Registers listed in Table 3-9 are CPU registers and are selected by register index numbers. The registers are accessed through I/O memory locations 22h and 23h. Registers are selected for access by writing ...

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Processor Programming Register (Index) Bit 7 Bit 6 Control Registers CCR1 (C1h) CCR2 (C2h) USE_SUSP CCR3 (C3h) LSS_34 LSS_23 CCR4 (E8h) CPUID SMI_NEST CCR7 (EBh) PCR0 (20h) LSSER RSVD PCR1 (F0h) SMM Base Header Address Registers SMHR0 (B0h ...

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Processor Programming Bit Name Description Index C1h 7:3 RSVD Reserved: Set to 0. 2:1 SMAC System Management Memory Access 00: SMM is disabled 01: SMI# pin is active to enter SMM. SMINT instruction is inactive. If ...

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Processor Programming Table 3-11. Configuration Registers (Continued) Bit Name Description Index E8h 7 CPUID Enable CPUID Instruction The ID bit in the EFLAGS register can be modified and execution of the CPUID instruction occurs as documented in ...

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Processor Programming Table 3-11. Configuration Registers (Continued) Bit Name Description Index 20h 7 LSSER Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory mapped I/O devices operating outside of the address range 640 ...

Page 56

... Reserved Index FFh 7:0 DIR1 Device Identification Revision (Read Only): DIR1 indicates device revision number. If DIR1 is 8xh = GX1 processor. See device errata for "x" value for each revision of silicon. www.national.com (Continued) DIR0: Device Identification Register 0 (RO) DIR1: Device Identification Register 1 (RO) ...

Page 57

... Processor Programming 3.3.2.3 Debug Registers Six debug registers (DR0-DR3, DR6 and DR7) support debugging on the GX1 processor. Memory addresses loaded in the debug registers, referred to as “breakpoints,” generate a debug exception when a memory access of the specified type occurs to the specified address. A break- point can be specified for a particular kind of memory access such as a read or write operation ...

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Processor Programming The Debug Status Register (DR6) reflects conditions that were in effect at the time the debug exception occurred. The contents of the DR6 register are not automatically cleared by the processor after a debug exception occurs, and therefore ...

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Processor Programming 3.3.2.4 TLB Test Registers Two test registers are used in testing the processor’s Trans- lation Lookaside Buffer (TLB), TR6 and TR7. Table 3- register map for the TLB Test Registers with their bit defini- tions given ...

Page 60

Processor Programming Bit Name Description TR7 Register 31:12 Physical Physical Address: Address TLB lookup: Data field from the TLB. TLB write: Data field written into the TLB. 11:10 RSVD Reserved: Set to 0. 9:7 TLB LRU LRU Bits: TLB lookup: ...

Page 61

Processor Programming 3.3.2.5 Cache Test Registers Three test registers are used in testing the processor’s on- chip cache, TR3-TR5. Table 3- register map for the Cache Test Registers with their bit definitions given in Table 3-17 on page ...

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Processor Programming Bit Name Description TR5 Register (R/W) 31:12 RSVD Reserved 11:4 Line Selection Line Selection: Physical address bits [11:4] used to select one of 256 lines. 3:2 Set/DWord Set/DWORD Selection: Selection Cache read: Selects which of the four sets ...

Page 63

Processor Programming There are five types of test operations that can be exe- cuted: • Flush buffer read • Fill buffer write • Cache write • Cache read • Cache flush Test Operation Code Sequence Flush Buffer Read MOV TR5, ...

Page 64

... During a MSR write, the contents of EDX:EAX are loaded into the MSR specified in the ECX register. The RDMSR and WRMSR instructions are privileged instructions. The GX1 processor contains one 64-bit Model Specific Register (MSR10) the Time Stamp Counter (TSC). www.national.com (Continued) 3.3.4 ...

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... KB). The CPU does not use coproces- sor communication space in upper I/O space between 800000F8h and 8000 00FFh as do the 386-style CPUs. The I/O locations 22h and 23h are used for GX1 processor configuration register access. 3.4.1 I/O Address Space The CPU I/O address space is accessed using IN and OUT instructions to addresses referred to as “ ...

Page 66

Processor Programming 3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS The mapping of address space into a sequence of memory locations (often cached) is performed by the offset, seg- ment, and paging mechanisms. In general, the offset, segment and paging mechanisms work ...

Page 67

Processor Programming 3.5.2 Segment Mechanisms Memory is divided into contiguous regions called “seg- ments.” The segments allow the partitioning of individual elements of a program. Each segment provides a zero address-based private memory for such elements as code, data, and ...

Page 68

Processor Programming 3.5.2.4 Segment Selectors The segment registers are used to store segment selec- tors. In protected mode, the segment selectors are divided in to three fields: the RPL, TI and INDEX fields as shown in Figure 3-6 on page ...

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Processor Programming Selector Load Instruction 15 Selector INDEX TI RPL In Segment Register Revision 4.1 (Continued) 0 Segment Descriptor Global Descriptor Table Segment Descriptor Local Descriptor Table Figure 3-7. Selector Mechanism Caching 69 Segment ...

Page 70

Processor Programming 3.5.3 Descriptors 3.5.3.1 Global and Local Descriptor Table Registers The GDT and LDT descriptor tables are defined by the Glo- bal Descriptor Table Register (GDTR) and the Local Descriptor Table Register (LDTR), respectively. Some texts refer to these ...

Page 71

Processor Programming 3.5.3.3 Task, Gate, Interrupt, and Application and System Descriptors Besides segment descriptors there are descriptors used in task switching, switching between tasks with different prior- ity and those used to control interrupt functions: • Interrupt Descriptors • Application ...

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Processor Programming Memory Bit Offset Name Description 31:24 +4 BASE Segment Base Address: Three fields which collectively define the base location for the segment physical address space. 7:0 +4 31:16 +0 19:16 +4 LIMIT Segment Limit: Two ...

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Processor Programming Table 3-23. Application and System Segment Descriptors TYPE Bit Definitions TYPE System Segment and Gate Types Bits [11:8] Num SEWA 0 0000 1 0001 Available 16-Bit TSS 2 0010 3 0011 4 0100 5 0101 6 0110 16-Bit ...

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Processor Programming Gate Descriptors Four kinds of gate descriptors are used to provide protec- tion during control transfers: • Call gates • Trap gates • Interrupt gates • Task gates (For more information on protection refer to Section 3.9 "Protection" ...

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Processor Programming Task State Segments Descriptors The CPU enables rapid task switching using JMP and CALL instructions that refer to Task State Segment (TSS) descriptors. During a switch, the complete task state of the current task is stored in its ...

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Processor Programming Table 3-27. 16-Bit Task State Segment (TSS) Table 15 www.national.com (Continued) Selector for Task’s LDT FLAGS IP SS for Privilege Level 0 SP for Privilege Level ...

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Processor Programming 3.5.4 Paging Mechanism The paging mechanism translates a linear address to its corresponding physical address. If the required page is not currently present in RAM, an exception is generated. When the operating system services the exception, the required ...

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Processor Programming Along with the base address of the page table or the page frame, each DTE or PTE contains attribute bits and a present bit as illustrated in Table 3-28. If the present bit (P) is set in the ...

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... CPU. 3.6.1 Interrupts External events can interrupt normal program execution by using one of the three interrupt pins on the GX1 processor: • Non-maskable Interrupt (No pin, see note) • Maskable Interrupt (INTR pin) • SMM Interrupt (SMI# pin) Note: There is not an NMI pin on the GX1 processor ...

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Processor Programming 3.6.3 Interrupt Vectors When the CPU services an interrupt or exception, the cur- rent program’s instruction pointer and flags are pushed onto the stack to allow resumption of execution of the inter- rupted program. In protected mode, the ...

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... Debug traps for the previous instruction and next instructions are handled as the next priority. When NMI and maskable INTR interrupts are both detected at the same instruction boundary, the GX1 processor services the NMI interrupt first. The CPU checks for exceptions in parallel with instruction decoding and execution ...

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Processor Programming 3.6.5 Exceptions in Real Mode Many of the exceptions described in Table 3-29 "Interrupt Vector Assignments" on page 80 are not applicable in real mode. Exceptions 10, 11, and 14 do not occur in real mode. Other exceptions ...

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... Non-SMM Figure 3-9. System Management Memory Address Space Revision 4.1 (Continued) The GX1 processor extends System Management Mode to support the virtualization of many devices, including VGA video. The SMM mechanism can be triggered by I/O activ- ity and also by access to selected memory regions. For example, SMM interrupts are generated when VGA addresses are accessed ...

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Processor Programming 3.7.1 SMM Operation SMM execution flow is summarized in Figure 3-10. Entering SMM requires the assertion of the SMI# pin for at least two SYSCLK periods or execution of the SMINT instruction. For the SMI# signal or SMINT ...

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... Tables 3-34 and 3-35 show the SMM header. A memory address field has been added to the end (offset –40h) of the header for the GX1 processor. Memory data will be stored overlapping the I/O data, since these events cannot occur simultaneously. The I/O address is valid for both IN and OUT instructions, and I/O data is valid only for OUT ...

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Processor Programming Table 3-35. SMM Memory Space Header Description Name DR7 Debug Register 7: The contents of Debug Register 7. EFLAGS Extended Flags Register: The contents of Extended Flags Register. CR0 Control Register 0: The contents of Control Register 0. ...

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... Processor Programming 3.7.5 SMM Instructions The GX1 processor core automatically saves a minimal amount of CPU state information when entering SMM which allows fast SMM service routine entry and exit. After enter- ing the SMM service routine, the MOV, SVDC, SVLDT and SVTS instructions can be used to save the complete CPU state information ...

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... To exit the SMM service routine, an RSM instruction, rather than an IRET, is executed. The RSM instruction causes the GX1 processor core to restore the CPU state using the SMM header information and resume execution at the interrupted point. If the full CPU state was saved by the ...

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Processor Programming When SMI nesting is disabled, the processor holds off external SMI interrupts until the currently executing SMM code exits. When SMI nesting is enabled, the processor can proceed with the SMI. The SMM service routine will guarantee that ...

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... The state diagram shown in Figure 3-12 illustrates the vari- ous CPU states associated with SMM and Suspend mode. While in the SMM service routine, the GX1 processor core can enter Suspend mode either by (1) executing a halt (HLT) instruction or (2) by asserting the SUSP# input. ...

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... HALT AND SHUTDOWN The halt instruction (HLT) stops program execution and generates the Halt bus cycle on the PCI bus. The GX1 pro- cessor core then drives out a Stop Grant bus cycle and enters a low-power Suspend mode if the SUSP_HLT bit in CCR2 (Index C2h[3]) is set. SMI#, NMI, INTR with inter- rupts enabled (IF bit in EFLAGS = 1), or RESET forces the CPU out of the halt state ...

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... Initialization and Transition to Protected Mode The GX1 processor core switches to real mode immedi- ately after RESET. While operating in real mode, the sys- tem tables and registers should be initialized. The GDTR and IDTR must point to a valid GDT and IDT, respectively. The ...

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... V86 address mechanism and which programs use pro- tected mode addressing for each task. The GX1 processor also permits the use of paging when operating in V86 mode. Using paging, the 1 MB address space of the V86 task can be mapped to any region in the 4 GB linear address space ...

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... Processor Programming 3.11 FLOATING POINT UNIT OPERATIONS The GX1 processor contains an FPU that is x87 and MMX instruction-set compatible and adheres to the IEEE-754 standard. Because most applications that contain FPU instructions intermix with integer instructions, the GX1 pro- cessor’s FPU achieves high performance by completing integer and FPU operations in parallel ...

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Processor Programming Bit Name Description 1 FPU Tag Word Register (R/W) 15:14 TAG7 TAG7 Valid Zero Special Empty. 13:12 TAG6 TAG6 Valid Zero Special ...

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... UMA systems is reduced through the use of National Semiconductor’s Display Compression Technol- ogy (DCT) architecture. Figure 4-1 shows the major functional blocks of the GX1 processor and how the internal bus interface unit operates as the interface between the processor’s core units and the integrated functions ...

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... KB 1:0 GX GX1 Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled Scratchpad RAM and control registers start at GX_BASE = 40000000h. ...

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... Table 4-3 on page 100) PCI Access Available to the system Extended Memory System BIOS Video BIOS UMBs and Expansion ROMs VGA/MDA Frame Buffers (Soft VGA and/or PCA/ISA) Conventional Memory Figure 4-2. GX1 Processor Memory Space 98 FFFFFFFFh (4 GB) MAX (256 KB) FFFC0000h GX_BASE+8800000h GX_BASE+800000h GX_BASE+400000h GX_BASE+9000h GX_BASE+8500h ...

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... Integrated Functions (Continued) 4.1.2 Control Registers The control registers for the GX1 processor use the memory map, starting at GX_BASE+8000h (see Figure 4-2 on page 98). The space from GX_BASE+9000h to GX_BASE+4000000h is also mapped to the control regis- ters, but is undefined. The defined control registers will alias into this undefined spaced ...

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... Section 4.1.6 on page 102. If the graphics pipeline or National software is used, and it is desirable to use scratchpad RAM by software other than that supplied by National, please contact your local National Semiconductor technical support representative. 4.1.4.3 BLT Buffer Address registers, BitBLT, have been added to the front ...

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Integrated Functions (Continued) Table 4-4. L1 Cache BitBLT Register Summary 1 Mnemonic Name L1_BB0_BASE L1 Cache BitBLT 0 Base Address L1_BB0_POINTER L1 Cache BitBLT 0 Pointer L1_BB1_BASE L1 Cache BitBLT 1 Base Address L1_BB1_POINTER L1 Cache BitBLT 1 Pointer 1. ...

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... The solution is to make these instruc- tions generate an illegal opcode trap unless a compatibil- ity bit is explicitly set. The GX1 processor uses the scratchpad size field (bits [3:2] in GCR, Index B8h) to enable or disable all of the graphics instructions. ...

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... If the NE bit is active, the IRQ13 output of the GX1 processor is always driven inac- tive. If the NE bit is cleared, the GX1 processor drives IRQ13 active when the ES bit (bit 7) in the FPU Status reg- ister is set high. Software must respond to this interrupt with an OUT instruction containing an 8-bit operand to F0h or F1h ...

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Integrated Functions (Continued) 4.2.5 Internal Bus Interface Unit Registers The internal bus interface unit maps 100h bytes starting at GX_BASE+8000h. However, only 16 bytes (four 32-bit reg- isters) are defined and some of these registers will alias across the 100h ...

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Integrated Functions (Continued) Table 4-9. Internal Bus Interface Unit Registers Bit Name Description GX_BASE+8000h-8003h 31:29 RSVD Reserved: Set to 0. 28:17 TOP OF Top of DRAM: DRAM 000h = Minimum top or 0001FFFFh (128 KB) FFFh = Maximum top or ...

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Integrated Functions (Continued) Table 4-9. Internal Bus Interface Unit Registers Bit Name Description GX_BASE+8008h-800Bh 31: Region: Region control field for address range DC000h to DFFFFh. 27: Region: Region control field for address range D8000h to DBFFFh. ...

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... The memory controller arbitrates requests from the X-Bus (processor and PCI), display controller, and graphics pipe- line. A total of 512 MB of SDRAM memory is supported. The GX1 processor supports LVTTL (low voltage TTL) technology. LVTTL technology allows the SDRAM interface of the memory controller to run at frequencies over 100 MHz ...

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... DIMM bank is selected by a unique chip select (CS). There are four chip select signals to choose between a total of four DIMM banks. Each DIMM bank also receives a unique SDCLK. Each DIMM bank can have two or four component Geode™ GX1 Processor www.national.com banks. Component bank selection is done through the bank address (BA) lines ...

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... Revision 4.1 that when using x4 SDRAM, there are 16 devices per bank. The GX1 supports a total of 32 devices. There are only two banks total when x4 devices are used. Row Column Address Address A10-A0 A7-A0 A10-A0 A8-A0 ...

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Integrated Functions (Continued) 4.3.3 SDRAM Commands This subsection discusses the SDRAM commands sup- ported by the memory controller. Table 4-12 summarizes these commands followed by detailed operational informa- tion regarding each command. Refer to the SDRAM manu- facturer’s specification for ...

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Integrated Functions (Continued) ACT — The activate command is used to open a row in a particular bank for a subsequent access. The value on the BA lines selects the bank, and the address on the MA lines selects the ...

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Integrated Functions (Continued) 4.3.4 Memory Controller Register Description The Memory Controller maps 100h locations starting at GX_BASE+8400h. However, only 28 bytes are defined and some of these registers will alias across the 100h space. Table 4-14. Memory Controller Register Summary ...

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Integrated Functions (Continued) Bit Name Description GX_BASE+ 8400h-8403h 31:29 RSVD Reserved 28:26 RSVD Reserved 25:23 RSVD Reserved 22 RSVD Reserved: Set RSVD Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles ...

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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description GX_BASE+8404h-8407h 31:14 RSVD Reserved: Set to 0. 13:11 RSVD Reserved 10 SDCLKOMSK# Enable SDCLK_OUT: Turn on the output Enabled Disabled. 9 SDCLK3MSK# Enable SDCLK3: ...

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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description 12 DIMM0_ DIMM0 Component Banks (Banks 0 and 1): Selects the number of component banks per module COMP_BNK bank for DIMM0 Component banks 1 = ...

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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description 7 RSVD Reserved: Set to 0. 6:4 DPL Data-in to PRE command period (tDPL): Minimum number of SDRAM clocks from the time the last write datum is sampled ...

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Integrated Functions (Continued) 4.3.5 Address Translation The memory controller supports two address translations depending on the method used to interleave pages. The hardware automatically enables high order interleaving. Low order interleaving is automatically enabled only under specific memory configurations. 4.3.5.1 ...

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Integrated Functions (Continued) Table 4-16. Auto LOI -- 2 DIMMs, Same Size, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A24 -- A25 MA11 A23 -- A24 MA10 A22 ...

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Integrated Functions (Continued) Table 4-18. Non-Auto LOI -- DIMMs, Different Sizes, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A23 -- A24 MA11 A22 -- A23 ...

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Integrated Functions (Continued) 4.3.6 Memory Cycles Figures 4-5 through 4-8 illustrate various memory cycles that the memory controller supports. The following subsec- tions describe some of the supported cycles. SDCLK CS# RAS# CAS# WE# MA DQM MD Figure 4-5. Basic ...

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Integrated Functions (Continued) SDRAM Write Cycle Figure 4-6 shows a SDRAM write cycle. The burst length for the WRT command is two. SDCLK CS# RAS# CAS# WE DQM Revision 4.1 COL n n n+1 n n+1 Figure 4-6. ...

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Integrated Functions (Continued) SDRAM Refresh Cycle Figure 4-7 shows a SDRAM auto refresh cycle. The mem- ory controller always precedes the refresh cycle with a PRE command to all banks. SDCLK CS# RAS# CAS# WE# MA[10] SDCLK COMMAND PRE NOP ...

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... Integrated Functions (Continued) 4.3.7 SDRAM Interface Clocking The GX1 processor drives the SDCLK to the SDRAMs; one for each DIMM bank. All the control, data, and address signals driven by the memory controller are sampled by the SDRAM at the rising edge of SDCLK. SDCLKOUT is a ref- erence signal used to generate SDCLKIN ...

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... Figure 6-10 and Figure 6-11 on page 201). Figure 4-10 shows an example of how the SHFTSDCLK bits setting affects SDCLK. The PCI clock is the input clock to the GX1 processor. The core clock is the internal proces- sor clock that is multiplied up. The memory controller runs PCI Clock ...

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... Integrated Functions (Continued) 4.4 GRAPHICS PIPELINE The graphics pipeline of the GX1 processor contains a 2D graphics accelerator. This hardware accelerator has a Bit- BLT/vector engine which dramatically improves graphics performance when rendering and moving graphical objects. Overall operating system performance is improved as well. The accelerator hardware supports pattern gener- ation, source expansion, pattern/source transparency, and 256 ternary raster operations ...

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... The pattern hardware, however, does not maintain a pat- tern origin, so the pattern data must be justified before it is loaded into the GX1 processor’s registers. For solid primi- tives, the pattern hardware is disabled and the pattern color is always sourced from the GP_PAT_COLOR_0 reg- ister (GX_BASE+8110h) ...

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Integrated Functions (Continued) 4.4.3.1 Monochrome Patterns Setting the pattern mode to 01b (GX_BASE+8200h[9:8] = 01b) in the GP_RASTER_MODE register selects the monochrome patterns (see bit details on page 132). Those pixels corresponding to a clear bit (0) in the pattern ...

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Integrated Functions (Continued) 4.4.3.3 Color Patterns Setting the pattern mode to 11b (GX_BASE+8200h[9:8] = 11b), in the GP_RASTER_MODE register selects the color patterns. Bits [63:0] are used to hold a row of pattern data for an 8-bpp pattern, with bits ...

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Integrated Functions (Continued) 4.4.6 Graphics Pipeline Register Descriptions The graphics pipeline maps 200h locations starting at GX_BASE+8100h. However, only 72 bytes are defined and some of these registers will alias across the 200h space. Table 4-23. Graphics Pipeline Configuration Register ...

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Integrated Functions (Continued) Table 4-23. Graphics Pipeline Configuration Register Summary (Continued) GX_BASE+ Memory Offset Type Name / Function 8208h-820Bh R/W GP_BLT_MODE Graphics Pipeline BLT Mode Register: Writing to this initiates a BLT operation. 820Ch-820Fh R/W GP_BLT_STATUS Graphics Pipeline BLT Status ...

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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+810Ch-810Dh 15:0 8-bpp Mode: 8-bpp color: The color index must be duplicated in the upper byte. 16-bpp Mode: 16-bpp color (RGB) GX_BASE+810Eh-810Fh 15:0 8-bpp Mode: 8-bpp color: ...

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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+8200h-8203h 31:13 RSVD Reserved: Set Transparent BLT: When set, this bit enables transparent BLT. The source color data will be compared to a ...

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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+820Ch-820Fh 31:11 RSVD Reserved: Set to 0. 10:9 W Screen Width: Selects a frame-buffer width. This register must be programmed correctly in order for com- pression to ...

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... DISPLAY CONTROLLER The GX1 processor incorporates a display controller that retrieves display data from the memory controller and for- mats it for output on a variety of display devices. The GX1 processor connects directly to the graphics Geode I/O companion. The display controller includes a display FIFO, ...

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... The compression algorithm used in the GX1 processor commonly achieves compression ratios between 10:1 and 20:1, depending on the nature of the display data. This ...

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... CRT display devices since flat panel displays have fixed resolutions and do not provide for overscan. When a display mode is selected having a lower resolution than the panel resolution, the GX1 proces- sor supports a mechanism to center the display by stretch- ing the border to fill the remainder of the screen. The border color is at palette extension 104h ...

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Integrated Functions (Continued) Simultaneous Resolution Colors 8-bpp 5 640x480 256 colors out of a palette of 256 16-bpp 64 KB colors 5-6-5 5 8-bpp 800x600 256 colors out of a palette of 256 16-bpp 64 KB Colors 5-6-5 1024x768 8-bpp ...

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Integrated Functions (Continued) Table 4-26. CRT and TFT Panel Data Bus Formats Panel Data CRT & Bus Bit 18-Bit TFT ...

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Integrated Functions (Continued) Resolution 640x480 8-bpp 256 colors out of a palette of 256 16-bpp 64 KB colors RGB 5-6-5 800x600 8-bpp 256 colors out of a palette of 256 16-bpp 64 KB colors RGB 5-6-5 1024x768 8-bpp 256 colors ...

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... Integrated Functions (Continued) 4.5.7 Graphics Memory Map The GX1 processor supports a maximum graph- ics memory and will map address space (see Fig- ure 4-2 on page 98) higher than the maximum amount of installed RAM. The graphics memory aperture physically resides at the top of the installed system RAM. The start address and size of the graphics memory aperture are pro- grammable on 512 KB boundaries ...

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... 10, 11, and 12. Likewise, the hardware can directly display all of the higher-resolution VESA modes. Since the frame buffer data is written directly to memory instead of travelling across an external bus, the GX1 pro- cessor often outperforms VGA cards for these modes. The display controller, however, does not directly support text modes ...

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Integrated Functions (Continued) Table 4-28. Display Controller Register Summary (Continued) GX_BASE+ Memory Offset Type Name/Function 8320h-8323h R/W DC_VID_ST_OFFSET Display Controller Video Start Address: Specifies offset at which the video buffer starts. 8324h-8327h R/W DC_LINE_DELTA Display Controller Line Delta: Stores line ...

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Integrated Functions (Continued) Table 4-28. Display Controller Register Summary (Continued) GX_BASE+ Memory Offset Type Name/Function Cursor and Line Compare Registers 8350h-8353h R/W DC_CURSOR_X Display Controller Cursor X Position: X position information of the hard- ware cursor. 8354h-8357h RO DC_V_LINE_CNT Display ...

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Integrated Functions (Continued) 4.5.8.1 Configuration and Status Registers The Configuration and Status registers group consists of four 32-bit registers located at GX_BASE+8300h-830Ch. Table 4-29. Display Controller Configuration and Status Registers Bit Name Description GX_BASE+8300h-8303h 31:16 RSVD Reserved: Set to 0. ...

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Integrated Functions (Continued) Table 4-29. Display Controller Configuration and Status Registers (Continued) Bit Name Description 11:8 DFIFO Display FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit HI-PRI entries which ...

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... DDC Clock: This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexed onto the CRT_VSYNC pin, but in order for it to have an effect, the VSYE bit[1] must be set low to disable the normal vertical sync. Software should then pulse this bit high and low to clock data into the GX1 pro- cessor. ...

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Integrated Functions (Continued) Table 4-29. Display Controller Configuration and Status Registers (Continued) Bit Name Description 3 BLKE Blank Enable: Allow generation of the composite blank signal to the display device Disable Enable. When disabled, the ENA_DISP ...

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... Integrated Functions (Continued) 4.5.9 Memory Organization Registers The GX1 processor utilizes a graphics memory aperture that size. The base address of the graphics memory aperture is stored in the DRAM controller Graph- ics Base Address register MC_GBASE_ADD register, Table 4-15 on page 116). The graphics memory is made up of the normal uncompressed frame buffer, compressed display buffer, and cursor buffer ...

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Integrated Functions (Continued) Table 4-30. Display Controller Memory Organization Registers (Continued) Bit Name Description GX_BASE+8324h-8327h 31:23 RSVD Reserved: Set to 0. 22:12 CB_LINE_ Compressed Display Buffer Line Delta: This value represents number of DWORDs that, when added to DELTA the ...

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Integrated Functions (Continued) 4.5.10 Timing Registers The Display Controller’s timing registers control the gener- ation of sync, blanking, and active display regions. They provide complete flexibility in interfacing to both CRT and flat panel displays. These registers will generally be ...

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Integrated Functions (Continued) Table 4-31. Display Controller Timing Registers (Continued) Name Bit Description GX_BASE+8338h-833Bh 31:27 RSVD Reserved: Set to 0. 26:19 H_SYNC Horizontal Sync End: The character clock count at which the CRT horizontal sync signal becomes inac- _END tive ...

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Integrated Functions (Continued) Table 4-31. Display Controller Timing Registers (Continued) Name Bit Description GX_BASE+8348h-834Bh 31:27 RSVD Reserved: Set to 0. 26:16 V_SYNC_E Vertical Sync End: The line at which the CRT vertical sync signal becomes inactive minus 1. ND 15:11 ...

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Integrated Functions (Continued) 4.5.11 Cursor Position and Miscellaneous Registers The Cursor Position registers contain pixel coordinate information for the cursor. These values are not latched by the timing generator until the start of the frame to avoid tearing artifacts when ...

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... Palette Access Registers These registers are used for accessing the internal palette RAM and extensions. In addition to the standard 256 entries for 8-bpp color translation, the GX1 processor pal- ette has extensions for cursor colors and overscan (border) color. Bit ...

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Integrated Functions (Continued) 4.5.13 FIFO Diagnostic Registers The FIFO Diagnostic register group consists of two 32-bit registers located at GX_BASE+8378h Bit Name Description GX_BASE+8378h-837Bh DC_DFIFO_DIAG Register (R/W) Default Value = xxxxxxxxh 31:0 DISPLAY FIFO Display FIFO Diagnostic Read or Write ...

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... Geode™ CS5530A I/O Companion Figure 4-16. Display Controller Signal Connections www.national.com Because the GX1 processor is used in a system with the CS5530A I/O companion chip, the need for an external RAMDAC is eliminated. The CS5530A contains the DACs, a video accelerator engine, and a TFT interface. ...

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... Figure 4-17. Video Port Data Transfer (CS5530A) Revision 4.1 VID_DATA[7:0] is advanced when both VID_VAL and VID_RDY are asserted. VID_RDY is driven one clock early to the GX1 processor while VID_VAL is driven coincident with VID_DATA[7:0]. A sample interface functional timing diagram is shown in Figure 4-17. 8 CLKs ...

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... Several functions can be virtualized in a GX1 processor based design using the VSA environment. The VSA enhanced Geode I/O companions provide programmable resources to trap both memory and I/O accesses. How- ...

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Integrated Functions (Continued) Category Mode Software 0,1 2,3 4 Hardware 0Dh 0Eh 0Fh 10h 11h 12h 13h A VGA is made up of several functional units. • The frame buffer is 256 KB of memory that provides data ...

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... Most of the front end functionality is implemented in the VGA read and write hardware of the GX1 processor. An important axiom of the VGA is that the front end and back end are controlled independently. There are no register fields that control the behavior of both pieces. Terms like “ ...

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... Virtual VGA The GX1 processor reduces the burden of legacy hard- ware by using a balanced mix of hardware and software to provide the same functionality. The graphics pipeline con- tains full hardware support for the VGA “front-end”, the logic that controls read and write operations to the VGA frame buffer (located in graphics memory) ...

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... GX1 processor. The VGA address generator requires the address from the VGA access (A0000h to BFFFFh), the base of the VGA memory on the GX1 pro- cessor, and various control bits. The control bits are neces- sary because addressing is complicated by odd/even and Chain 4 addressing modes ...

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... DRAM, starting at zero and ending at memory size. Graphics memory is mapped into high physical memory, contiguous to the registers and ded- icated cache of the GX1 processor. The graphics memory includes the frame buffer, compression buffer, cursor mem- ory, and VGA memory. The VGA memory is mapped on a 256 KB boundary to simplify the address generation 4 ...

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Integrated Functions (Continued) Bit Description Index B9h 7:3 Reserved: Set SMI generation for VGA memory range B8000h to BFFFFh Disable Enable. 1 SMI generation for VGA memory range B0000h to B7FFFh ...

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Integrated Functions (Continued) 4.6.4 Virtual VGA Register Descriptions This section describes the registers contained in the graph- ics pipeline used for VGA emulation. The graphics pipeline maps 200h locations starting at GX_BASE+8100h. Refer GX_BASE+ Memory Offset Type Name/Function 8140h-8143h R/W ...

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Integrated Functions (Continued) Bit Name Description GX_BASE+8140h-8143h 31:28 RSVD Reserved: Set to 0. 27:24 MAP_MASK Map Mask: Enables planes 3 through 0 for writing. Combined with chain control to determine the final enables. 23:21 RSVD Reserved: Set ...

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... PCI Specification 2.1 and briefly described here. To initiate a special cycle from software, the host must write a value to CONFIG_ADDRESS encoded as shown in Table 4-40. The next value written to CONFIG_DATA is the encoded special cycle. Type 0 or Type 1 conversion will be based on the Bus Bridge number matching the GX1 processor’s bus ...

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... DEVICE Device: Selects a device on a specified bus. A device value of 00h will select the GX1 processor if the bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 of the 32 possi- ble devices are supported. A DEVICE value of 00001b will map to AD[11] while a device of 10101b will map to AD[31] ...

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... PCI Configuration Space Registers To access the internal PCI configuration registers of the GX1 processor, the Configuration Address register (CONFIG_ADDRESS) must be written as a DWORD using the format shown in Table 4-42. Any other size will be inter- preted as an I/O write to Port 0CF8h. Also, when entering the Configuration Index, only the six most significant bits of Table 4-42 ...

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... This bit can be cleared writing it. 11 STA Signaled Target Abort: This bit is set whenever the GX1 processor signals a target abort. A target abort is signaled when an address parity occurs for an address that hits in the GX1 processor’s address space. This bit can be cleared writing it. ...

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... Table 4-44. PCI Configuration Registers (Continued) Bit Name Description 10:9 DT Device Timing: The GX1 processor performs medium DEVSEL# active for addresses that hit into the GX1 processor address space. These two bits are always set to 01 Fast 01 = Medium 10 = Slow 11 = Reserved 8 DPD Data Parity Detected: This bit is set when all three conditions are met ...

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... X-Bus to PCI Write Buffer: Enable GX1 processor PCI master’s X-Bus write buffers (non-locked memory cycles are buffered, I/O cycles and lock cycles are not buffered Disable Enable. 3:2 SDB Slave Disconnect Boundary: GX1 as a PCI slave issues a disconnect with burst data when it crosses line boundary 128 bytes 01 = 256 bytes ...

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Integrated Functions (Continued) Table 4-44. PCI Configuration Registers (Continued) Bit Name Description Index 44h 7 PP Ping-Pong Arbiter grants the processor bus per the setting of bits [2:0 Arbiter grants the processor bus ownership of the ...

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Integrated Functions (Continued) 4.7.8 PCI Cycles The following sections and diagrams provide the functional relationships for PCI cycles. 4.7.8.1 PCI Read Transaction A PCI read transaction consists of an address phase and one or more data phases. Data phases may ...

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Integrated Functions (Continued) 4.7.8.2 PCI Write Transaction A PCI write transaction is similar to a PCI read transaction, consisting of an address phase and one or more data phases. Since the master provides both address and data, no turnaround cycle ...

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... Agent A by asserting GNT#-a on CLK 2. Agent A must begin a transaction by asserting FRAME# within 16 clocks, or the GX1’s PCI arbiter will remove GNT#. Also possible for Agent A to lose bus ownership sooner if another agent with higher priority requests the bus. How- ever, in this example, Agent higher priority than Agent A ...

Page 177

... Suspend-on-Halt Suspend-on-Halt is the most effective power reducing fea- ture of the GX1 processor with the system active. This fea- ture allows the system to reduce power when the system’s OS becomes idle without producing any delay when the system’s OS becomes active. ...

Page 178

... CPU status to the Geode I/O companion. The GX1 processor accumulates CPU events in a 8-bit register, “PM Serial Packet” register (GX_BASE+850Ch), that is serially transmitted out of the GX1 processor every µ s. The transmission frequency is set with bits [4:3] of the “PM Serial Packet Control” register. These register formats are given in Table 5-2 on page 184 ...

Page 179

Power Management (Continued) 5.2 SUSPEND MODES AND BUS CYCLES The following subsections describe the bus cycles of the various Suspend states. 5.2.1 Timing Diagram for Suspend-on-Halt The CPU enters Suspend-on-Halt as a result of executing a halt (HLT) instruction if ...

Page 180

... Power Management (Continued) 5.2.2 Initiating Suspend with SUSP# The GX1 processor enters the Suspend mode in response to SUSP# input assertion only when certain conditions are met. First, the USE_SUSP bit must be set in CCR2 (Index C2h[7]). In addition, execution of the current instructions and any pending decoded instructions and associated bus cycles must be completed ...

Page 181

... Power Management (Continued) 5.2.3 Stopping the Input Clock The GX1 processor is a static device, allowing the input clock (SYSCLK stopped and restarted without any loss of internal CPU data. The SYSCLK input can be stopped at either a logic high or logic low state. The required sequence for stopping SYSCLK is to initiate 3 Volt Suspend, wait for the assertion of SUSPA# by the proces- sor, and then stop the input clock ...

Page 182

... Power Management (Continued) 5.3 POWER MANAGEMENT REGISTERS The GX1 processor contains the power management reg- isters for the serial packet transmission control, the user- defined power management address space, Suspend Refresh, and SMI status for Suspend/Resume. The power management registers are mapped to A00h locations start- ing at GX_BASE+8500h ...

Page 183

... Volt Suspend Mode. The external clock may be stopped during Suspend. Note: When bit 0 is set high and the Suspend input pin (SUSP#) is asserted, the GX1 processor stops all it’s internal clocks, and asserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GX1 processor’s SYSCLK input can be stopped ...

Page 184

... This bit has a corresponding enable bit in the PM_CNTRL_TEN. Note: The GX1 processor transmits the contents of the serial packet only when a bit in the packet register is set and the interval counter has elapsed. The Geode I/O companion decodes the serial packet after each transmission. Once a bit in the packet is set, it will remain set until the completion of the next packet transmission ...

Page 185

... Core Voltage (V Part Marking CC2 GX1-333P-85-2.2 2.2V (Nominal) GX1-333B-85-2.2 GX1-300P-85-2.0 2.0V (Nominal) GX1-300B-85-2.0 GX1-266P-85-1.8 1.8V (Nominal) GX1-266B-85-1.8 GX1-233P-85-1.8 GX1-233B-85-1.8 GX1-200P-85-1.8 GX1-200B-85-1.8 1. Typical power consumption is defined as an average measured running Windows at 80% Active Idle (Suspend-on-Halt) with a display resolution of 800x600x8 bpp at 75 Hz. ...

Page 186

... ELECTRICAL CONNECTIONS 6.2.1 Power/Ground Connections and Decoupling Testing and operating the GX1 processor requires the use of standard high frequency techniques to reduce parasitic effects. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low-impedance wiring, and by connecting all V and V pins to the appropriate voltage levels ...

Page 187

... Figure 6-2. SPGA Recommended Split Power Plane and Decoupling Revision 4.1 3.3V Plane (V ) CC3 1.8V, 2.0V, or 2.2V Plane (V ) CC2 Geode™ GX1 Processor 320 SPGA - Top View 1.8V, 2.0V, or 2.2V Plane (V ) CC2 3.3V Plane (V ) CC3 Note: Where signals cross plane splits recommended to include AC decoupling between planes with 47 pF capacitors ...

Page 188

... ABSOLUTE MAXIMUM RATINGS Table 6-3 lists absolute maximum ratings for the GX1 proces- sor. Stresses beyond the listed ratings may cause permanent damage to the device. Exposure to conditions beyond these lim- its may (1) reduce device reliability and (2) result in prema- ture failure even when there is no immediately apparent sign of failure ...

Page 189

... Electrical Specifications (Continued) 6.4 OPERATING CONDITIONS Table 6-4 lists the operating conditions for the GX1 processor. Symbol Parameter T Operating Case Temperature Core Supply Voltage CC2 1.8V (Nominal 200, 233, or 266 MHz CLK 2.0V (Nominal 300 MHz CLK 2.2V (Nominal 333 MHz ...

Page 190

... Table 6-4 "Operating Conditions" on page 189. 6.5.1 Input/Output DC Characteristics Table 6-5 shows the input/output DC parameters for all devices in the GX1 processor series. 6.5.2 DC Current DC current is not a simple measurement. The CPU has four power states and two functional characteristics that determine how much current the processor uses at any given point in time ...

Page 191

... MHz (8x)/3.0 = 88.9 MHz 300 MHz (9x)/3.0 = 100.0 MHz 333 MHz (10x)/3.0 = 111.0 MHz Note: Not all configurations listed here are supported. Refer to the document titled “Geode™ GX1 Processor Series: Memory Timings for Maximum Performance” for supported configurations. Revision 4.1 • ...

Page 192

... DC Current Measurements The following tables show the DC current measurements for the 1.8V (Tables 6-7 and 6-8), 2.0V (Tables 6-9 and 6-10) and 2.2V (Tables 6-11 and 6-12) devices of the GX1 processor series. Table 6-7. 1.8V DC Characteristics for CPU Mode = “On” ...

Page 193

Electrical Specifications (Continued) Table 6-9. 2.0V DC Characteristics for CPU Mode = “On” 1 Symbol Parameter I I/O Current @ V = 3.3V (Nominal); CC3ON CC3 CPU mode = “On”; f CLK I Core Current @ V CC2ON CC2 CPU ...

Page 194

Electrical Specifications (Continued) Table 6-11. 2.2V DC Characteristics for CPU Mode = “On” 1 Symbol Parameter I I/O Current @ V = 3.3V (Nominal); CC3ON CC3 CPU mode = “On”; f CLK I Core Current @ V CC2ON CC2 CPU ...

Page 195

... I/O Current De-Rating Curve The I/O current de-rating curve, shown in Figure 6-3, is the same for all devices in the GX1 series of processors. While the memory speeds for the various core frequencies are different, the three memory speeds for each device pro- duce the same de-rating effect ...

Page 196

Electrical Specifications (Continued) 6.7 AC CHARACTERISTICS The following tables list the AC characteristics including output delays, input setup requirements, input hold require- ments, and output float delays. The rising-clock-edge refer- ence level V , and other reference levels are shown ...

Page 197

Electrical Specifications (Continued) Parameter 1 Setup Time for RESET, INTR 1 Hold Time for RESET, INTR Setup Time for SMI#, SUSP#, FLT# Hold Time for SMI#, SUSP#, FLT# Valid Delay for IRQ13 Valid Delay for SUSPA# Valid Delay for SERIALP ...

Page 198

Electrical Specifications (Continued) Symbol Parameter t SYSCLK Period 1 t SYSCLK Period Stability 2 t SYSCLK High Time 3 t SYSCLK Low Time SYSCLK Fall Time SYSCLK Rise Time 6 t SDCLK_OUT, SDCLK[3:0] Period ...

Page 199

Electrical Specifications (Continued IH(Min) 1.5V V IL(Max) SYSCLK t 6 Figure 6-6. SYSCLK Timing and Measurement Points (Min) 1. (Max) SDCLK_OUT, SDCLK[3: Figure 6-7. SDCLK[3:0] Timing and Measurement Points ...

Page 200

Electrical Specifications (Continued) Symbol Parameter t Delay Time, SYSCLK to Signal Valid for Bused Signals VAL1 t Delay Time, SYSCLK to Signal Valid for GNT# VAL2 t Delay Time, Float to Active ON t Delay Time, Active to Float OFF ...

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