SP692ACP Exar Corporation, SP692ACP Datasheet
SP692ACP
Related parts for SP692ACP
SP692ACP Summary of contents
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Low Power Microprocessor Supervisory FEATURES Precision Voltage Monitor: SP690A/SP802L/SP805L at 4.65V SP692A/SP802M/SP805M at 4.40V Reset Time Delay - 200ms Watchdog Timer - 1.6 sec timeout Minimum component count 60µA Maximum Operating Supply Current 0.6µA Maximum Battery Backup Current 0.1µA ...
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ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica- tions below is not implied. Exposure to absolute maxi- mum ...
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V =4.75v to 5.50V for SP690A/SP802L/SP805L unless otherwise noted ...
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V V OUT BATT 2 7 RESET (RESET GND 3 6 WDI PFI 4 PFO SP805 only Figure 10. Pinout PIN ASSIGNMENTS Pin 1 —V — Output Supply Voltage. V OUT connects to ...
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V Supply Current vs. CC Temperature (Normal Mode = =2.8V 47 BATT -60 - 120 150 Temperature Deg BATT OUT ...
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V =4. =0V BATT Slope=0.6Ω 100 IOUT (mA) Figure Vs. Output Current CC OUT div 0V RESET 0V 1sec/div Figure 3A. SP690A RESET Output Voltage vs. ...
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V CC +5V +4V RESET +5V 0V 2µs/div Figure 5A. SP690A RESET Response Time + +4V RESET +4V 0V 2µs/div Figure 6A. SP805L RESET Response Time +1.3V PFI +1.2V PFO 5V 0V 500ns/div Figure 7A. Power-Fail Comparator Response ...
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PFI +1.3V +1.2V 3V PFO 0V 2µs/div Figure 8A. Power-Fail Comparator Response Time (RISE) + +5V RESET* 0V +5V RESET** 0V +5V V OUT 0V +5V PFO PFI = 3.0V BATT Figure 9. Timing ...
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FEATURES The SP690A/692A/802L/802M/805L/805M provide four key functions battery backup switching for CMOS RAM, CMOS microprocessors, or other logic reset output during power-up, power-down and brownout conditions reset pulse if the optional watchdog timer has ...
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The SP805L/M active-high RESET output is the inverse of the SP690A/SP692A/SP802 RE- SET output, and is valid with V Some µP's, such as Intel's 80C51, require an active-high reset pulse. Watchdog Input The watchdog circuit monitors the µP's activity. If ...
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V CC PFI R 3 PFO connect to µP GND 1. TRIP ...
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V CC PFI PFO GND 1. 5 PFO + TRIP * negative voltage TRIP Figure 19. Monitoring a Negative Voltage Interfacing to Microprocessors with Bidirectional Reset Pins ...
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N INDEX AREA PIN PDIP JEDEC MS-001 (BA) Variation SYMBOL MIN 0.15 A2 0.115 b 0.014 b2 0.045 b3 0.3 c 0.008 D 0.355 D1 0.005 E 0.3 E1 0.24 ...
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D e E/2 1 INDEX AREA (D/2 X E1/2) TOP VIEW 8 Pin NSOIC JEDEC MO-012 (AA) Variation MIN SYMBOL A 1.35 A1 0.1 A2 1.25 b 0.31 c 0.17 D 4.90 BSC E 6.00 BSC E1 3.90 BSC e ...
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... SP690AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP SP692ACN........................................................0°C to +70°C......................................................8-Pin NSOIC SP692ACN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC SP692ACP........................................................0°C to +70°C.........................................................8-Pin PDIP SP692AEN......................................................-40°C to +85°C.....................................................8-Pin NSOIC SP692AEN/TR................................................-40°C to +85°C.....................................................8-Pin NSOIC SP692AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP SP802LCN........................................................0° ...