AT45DB161-RC ATMEL Corporation, AT45DB161-RC Datasheet

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AT45DB161-RC

Manufacturer Part Number
AT45DB161-RC
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
ATMEL Corporation
Datasheet
Features
Description
The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of
528 bytes each. In addition to the main memory, the AT45DB161 also contains two
SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash memo-
Pin Configurations
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Single 2.7V - 3.6V Supply
Serial Interface Architecture
Page Program Operation
Optional Page and Block Erase Operations
Two 528-Byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Internal Program and Control Timer
Fast Page Program Time – 7 ms Typical
120 s Typical Page to Buffer Transfer Time
Low Power Dissipation
13 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (528 Bytes/Page) Main Memory
– 4 mA Active Read Current Typical
– 3 A CMOS Standby Current Typical
Note: PLCC package pins 16
and 17 are DON’T CONNECT
SCK
SO
NC
NC
NC
NC
NC
NC
SI
5
6
7
8
9
10
11
12
13
Chip Select
Hardware Page
Write Protect Pin
Chip Reset
Ready/Busy
Function
Serial Clock
Serial Input
Serial Output
PLCC
29
28
27
26
25
24
23
22
21
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
RDY/BUSY
GND
SCK
RESET
NC
NC
SO
NC
NC
NC
NC
NC
NC
NC
CS
SI
GND
VCC
SCK
WP
NC
NC
NC
NC
NC
CS
SO
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TSOP Top View
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
Type 1
A
B
C
D
E
Through Package
CBGA Top View
NC
NC
NC
NC
1
SCK
NC
SO
NC
CS
2
(continued)
RDY/BSY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
NC
NC
3
SI
RESET
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
WP
NC
4
NC
NC
NC
NC
NC
5
16-Megabit
2.7-volt Only
Serial
DataFlash
AT45DB161
Preliminary
AT45DB161
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
Rev. 0807C–07/98
®
1

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AT45DB161-RC Summary of contents

Page 1

... The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-sys- tem reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes each. In addition to the main memory, the AT45DB161 also contains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...

Page 2

... Diagram illustrates the breakdown of each level and AT45DB161 2 To allow for simple in-system reprogrammability, the AT45DB161 does not require high input voltages for pro- gramming. The device operates from a single power sup operations. The AT45DB161 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...

Page 3

... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB161, the first two address bits are reserved for larger density devices (see Notes on page 10), the next 12 address bits ...

Page 4

... CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page AT45DB161 4 are internally self timed and should take place in a maxi- mum time of t ...

Page 5

Block Erase Addressing PA11 PA10 PA9 PA8 • • • • • • • • • • • • ...

Page 6

... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB161, the three bits are 1, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...

Page 7

... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB161 - 2.7V to 3.6V 7 ...

Page 8

... PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC Input Test Waveforms and Measurement Levels 2.4V AC DRIVING LEVELS 0.45V < (10 AT45DB161 8 Condition CS, RESET all inputs IH at CMOS levels MHz mA; OUT CMOS levels CMOS levels I 1.6 mA ...

Page 9

AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both ...

Page 10

... It is recommended that “r” logical “0” for densities of 16M bit or smaller. 3. For densities larger than 16M bit, the “r” bits become the most significant Page Address bit for the appropriate density. AT45DB161 10 tRST CMD 8 bits ...

Page 11

Write Operations The following block diagram and waveforms illustrate the various write sequences available. PAGE (528 BYTES) BUFFER 1 TO MAIN MEMORY PAGE PROGRAM BUFFER 1 (528 BYTES) BUFFER 1 WRITE Main Memory Page Program through Buffers ...

Page 12

... SO Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read Each transition represents 8 bits and 8 clock cycles AT45DB161 12 FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 X Starts reading page data into buffer CMD ...

Page 13

Detailed Bit-Level Read Timing – Inactive Clock Polarity Low Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read ...

Page 14

... Detailed Bit-Level Read Timing – Inactive Clock Polarity High Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK tSU HIGH-IMPEDANCE SO AT45DB161 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE DATA OUT MSB DATA OUT ...

Page 15

Table 1. Main Memory Buffer 1 Buffer 2 Page Read Read Read 52H 54H 56H ...

Page 16

... PA5 PA5 PA5 PA4 PA4 PA4 PA3 PA3 PA3 PA2 PA2 PA2 PA1 PA1 PA1 PA0 PA0 PA0 AT45DB161 16 Buffer 2 to Main Memory Page Program without Page Block Built-In Erase Erase Erase Opcode 89H 81H 50H PA11 PA11 PA11 PA10 PA10 ...

Page 17

Figure 1. Algorithm for Programming or Reprogramming of an Entire Sector Sequentially MAIN MEMORY PAGE PROGRAM Notes: 1. This type of algorithm is used for applications in which an entire sector is programmed sequentially, filling the sector page- by-page. 2. ...

Page 18

... Flash array. Low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all 256 pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB161 18 START provide address of page to modify ...

Page 19

... Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-Lead, Plastic Thin Small Outline Package (TSOP) 24C2 24-Ball Array Plastic Chip-Scale Ball Grid Array (CBGA) Standby Ordering Code 0.01 AT45DB161-JC AT45DB161-RC AT45DB161-TC AT45DB161-CC 0.01 AT45DB161-JI AT45DB161-RI AT45DB161-TI AT45DB161-CI Package Type ...

Page 20

Packaging Information 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45° PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...

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