MH89790B Zarlink Semiconductor, MH89790B Datasheet
MH89790B
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MH89790B Summary of contents
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... CEPT PCM 30/CRC-4 Framer & Interface MH89790B MH89790BN MH89790BS Description The MH89790B is Zarlink’s CEPT PCM 30 interface solution, designed to meet the latest CCITT standards PCM 30 format with CRC-4. MH89790B provides a complete interface between a 2.048 Mbit/sec digital trunk and Zarlink’s Telecom Bus, the ST-BUS. ...
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... MH89790B Pin Description Pin # Name 2 IC Internal Connection. Leave open circuit. 3 E2o 2048 kHz Extracted Clock (Output): This clock is extracted by the device from the received signal used internally to clock in data received at RxT and RxR D.C. Power Input. (+5V RxA Receive A (Output): The bipolar CEPT signal received by the device at the RxR and RxT inputs is converted to a unipolar format and output at this pin ...
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... Transmit Multiframe Boundary (Input): This input can be used to set the channel associated and CRC transmitted multiframe boundary (clear the frame counters transmit multiframe signal is not being generated externally to the device, the MH89790B will internally generate its own multiframe when this pin is tied high. ...
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... ST-BUS. This serial stream is divided into 125 µs frames that are made bit channels. The line interface to the MH89790B consists of split phase unipolar inputs and outputs which are supplied from/to a bipolar line receiver/driver, respectively. ...
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... Si2 Zarlink Semiconductor Inc. MH89790B frame pulse (F0i) Meaning CRC results for both SMFI, II are error free. CRC result for SMFII is in error. CRC result for SMFI is error free. CRC result for SMFII is error free. CRC result for SMFI is in error. ...
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... Most Significant Bit (First) Data Input (DSTi) The MH89790B receives information channels on the DSTi pin. Of the 32 available channels on this serial input, 30 are defined as information channels. They are channels 1-15 and 17-31. These 30 timeslots are the 30 telephone channels of the CEPT format numbered 1-15 and 16-30. ...
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... Data sheet Zarlink Semiconductor Inc. MH89790B 7 ...
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... Keep at ‘0‘ for normal operation. 5 CCS Common Channel Signalling then the MH89790B operates in its common channel signalling mode. Channel 16 on the DSTi pin is transmitted on timeslot 16 of the CEPT link, and timeslot 16 from the received CEPT link is output on channel 16 on the DSTo pin. Channel 15 on the CSTi0 pin contains the information for the control of timeslot 16 ...
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... Table 8 Non-Frame-Alignment Signal: Data Format for CSTi1 Channel 17 CSTi0 controls channel 1 of DSTi. Channels 15 and 31 of CSTi0 contain Master Control Words 1 and 2 (MCW1, MCW2) which are used to set up the interface feature as seen by the respective bit functions of Tables 3 and 4. DESCRIPTION DESCRIPTION DESCRIPTION Zarlink Semiconductor Inc. MH89790B 9 ...
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... MH89790B BIT NAME 7 N/A Keep at zero for normal operation. 6 SiMUX When set to ‘1’, this bit will cause the SMFI CRC result to be transmitted in the next outgoing Si1 bit in frame 13 and the SMFII CRC result to be transmitted in the next outgoing Si2 bit in frame 15 ...
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... National Use: These are the bits which are received on the CEPT 2048 kbit/s link in bit positions timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on crossing international borders they should have the value ‘1‘. Table 13 Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17 DESCRIPTION DESCRIPTION DESCRIPTION Zarlink Semiconductor Inc. MH89790B 11 ...
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... MH89790B. It goes to ‘0‘ when frame synchronization is detected. 6 MFSYN Multiframe Sync: This bit goes to ‘1‘ to indicate a loss of multiframe synchronization by the MH89790B. It goes to ‘0‘ when multiframe synchronization is detected. 5 ERR Frame Alignment Error: This bit changes state when 16 or more errors have been detected in the frame alignment signal ...
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... Phase Status Word. Elastic Buffer The MH89790B has a two frame elastic buffer at the receiver which absorbs the jitter and wander in the received signal. The received data is written into the elastic buffer with the extracted E2o (2048 kHz) clock and read out of the buffer on the ST-BUS side with the system C2i (2048 kHz) clock (e ...
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... If the first assumption holds and the bit error rate -3 is reasonable, (below 10 ) then the probability of two or more errors in 7 bits is very low. Attenuation ROM All transmit and receive data in the MH89790B is passed through the digital according to the values set on bits data channels in the control stream (CSTi0) ...
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... Input jitter tolerance of the MH89790B exceeds minimum jitter tolerance as specified in CCITT I.431 and G.823 (see Figure 13). out of synchronization No search for frame alignment signal Yes No verify bit 2 of non- ...
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... This clock is used to latch received data. The falling edge of E2o is approximately aligned with the center of the received data pulse. Alignment between these signals can be disrupted by jitter and wander on the received signal. Maximum MH89790B to the input jitter is shown in Figure 13 relative to minimum jitter tolerance specified in G.823 and I.431. 16 ➁ ...
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... Data sheet Zarlink Semiconductor Inc. MH89790B 17 ...
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... MH89790B 18 Zarlink Semiconductor Inc. Data sheet ...
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... Figure 15 illustrates a typical application of the MH89790B in an ISDN environment. Three types of information are passed through serial busses of the MH89790B: USER DATA - The data streams of the MH89790B are shown connected to the MT8980 Digital Crosspoint Switch. This allows voice and data channels to be switched dynamically within the system ...
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... Semiconductor has available CEPT MH89790B Ancilliary Component Kits which contains input and output transformers. Alternatively, they are available directly from the following manufacturer: Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 Telephone: 613-226-1626 ...
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... I 500 0 0. 319 † - Capacitance ‡ Sym Min Typ Max Zarlink Semiconductor Inc. MH89790B Min Max Units -0 -0 -40 85 °C 800 mW ) unless otherwise stated. SS Units Test Conditions ° For 400 mV noise margin V RxT and RxR V For 400 mV noise margin V RxT and RxR ...
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... MH89790B AC Electrical Characteristics Characteristics 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Hold Time 5 Frame Pulse Width 6 Serial Output Delay 7 Serial Input Setup Time 8 Serial Input Hold Time 9 Frame Pulse Setup Time 2 † Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ...
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... RMFD t 50 TMFS t 50 TMFH t 100 MF2S Bit 4 Bit 0 Bit 7 Bit 6 Frame N Bit 4 Bit 0 Bit 7 Bit 6 t RMFD t TMFH Zarlink Semiconductor Inc. MH89790B Max Units Test Conditions 150 ns 50pF Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 t MF2S 23 ...
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... MH89790B AC Electrical Characteristics Characteristics 1 External Control Delay 2 External Status Setup Time 3 External Status Hold Time 4 E8Ko Output Delay 5 E8Ko Output Low Width 6 E8Ko Output High Width 7 E8Ko Output Transition Time † Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ...
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... PEC t 244 WEC t 50 RDS t 50 RDH t 244 RDW t 20 RDF t 30 RDR Bit Cell t TSD Bit Cells t PEC t WEC t t RDS RDH t RSS Zarlink Semiconductor Inc. MH89790B Units Test Conditions ns See Figure 27, Note TSD t t TST TST t WEC t RSH 25 ...
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... MH89790B Figure 27 - OUTA and OUTB Test Circuit E2o HDB3 RxA RxB E8K0 C2i INT DATA OUTA OUTB HDB3 26 +5V • (+ 12V) 400Ω OUTA • • 50pF +5V (+ 12V) • • 400Ω OUTB • • 50pF 125µSec Figure 28 - CEPT Receive Timing Figure 29 - CEPT Transmit Timing Zarlink Semiconductor Inc ...
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... The MH89790BN which is a narrow version of the MH89790B and has a row pitch of 0.8”. See Figure 32 for the dimensional drawing for this part. • The MH89790BS which is a surface mountable version of the MH89790BN is suitable for Infrared Reflow (I.R.) soldering. See Figure 33 for the dimensional drawing, and Figure 34 for the recommended footprint ...
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... Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale. Figure 32 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch 2.0 (50.8) MH89790BS Note 1 Notes: 1) Pin 1 not fitted. 2) All dimensions are typical and in inches (mm). 3) Not to scale. ...
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... Data sheet Pin 2 position 0.090 (2.29) 0.040 (1.02) Figure 34 - Recommended Footprint for the 40 Pin Dual in Line S.M.T. Hybrid 0.760 (19.3) 0.060 (1.52) Zarlink Semiconductor Inc. MH89790B 29 ...
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... MH89790B Appendix Control and Status Register Summary 7 6 UNUSED LOOP16 1 Enabled Keep Disabled Master Control Word 1 (MCW1) - CSTi0, Channel 15 UNUSED UNUSED CCS 1 Common Keep at 1 Keep at 0 Channel 0 Channel Associated Master Control Word 2 (MCW2) - CSTi0, Channel 31 UNUSED SiMUX RMLOOP 1 Enabled 1 Enabled ...
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... CRC Error Counter - CSTo, Channel 20 D(N) A(N+15 Signalling Bit Signalling Bit FAF2-8 Received Frame Alignment Signal X1 International Bit Bits Reserved for National Use Zarlink Semiconductor Inc. MH89790B 2 1 TXTS16AIS XS UNUSED 1 Alarm 1 XSt High Detected 0 XSt Low 0 No Alarm CRC Ref CRC Sync FrmPhase ...
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... MH89790B 32 Zarlink Semiconductor Inc. Data sheet ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...