MC68HC705SR3P Motorola, MC68HC705SR3P Datasheet

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MC68HC705SR3P

Manufacturer Part Number
MC68HC705SR3P
Description
Manufacturer
Motorola
Datasheet

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MC68HC705SR3P
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MC68HC05SR3D/H
REV. 2
HC05
MC68HC05SR3
MC68HC705SR3
TECHNICAL
DATA
!MOTOROLA

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MC68HC705SR3P Summary of contents

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... HC05 MC68HC05SR3 MC68HC705SR3 TECHNICAL DATA MC68HC05SR3D/H !MOTOROLA REV. 2 ...

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GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TIMER MC68HC705SR3 TPG ...

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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS ...

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... All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available on request. ...

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Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; ...

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... CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05SR3D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...

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... Name: Position: Department: Company: Address: Thank you for helping us improve our documentation, HKG CSIC Technical Publications , Motorola Semiconductors H.K. Ltd., Hong Kong. Excellent Poor 3–5 years More than 5 years – Second fold back along this line – Motorola Semiconductors H.K. Ltd., ...

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... Port A — Keyboard Interrupts (KBI) ......................................................................3-2 3.3 PD0:PD5 — ADC Inputs........................................................................................3-2 3.4 PD6 — IRQ2..........................................................................................................3-3 3.5 Programmable Current Drive .................................................................................3-3 3.6 Programmable Pull-Up Devices.............................................................................3-5 3.6.1 Port Option Register ........................................................................................3-5 MC68HC05SR3 TITLE 1 GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS Page Number TPG MOTOROLA i ...

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... Operation during Low Power Modes .....................................................................6-4 ANALOG TO DIGITAL CONVERTER 7.1 ADC Operation ......................................................................................................7-2 7.2 ADC Status and Control Register (ADSCR)..........................................................7-3 7.3 ADC Data Register (ADDR) ..................................................................................7-4 7.4 ADC during Low Power Modes..............................................................................7-4 MOTOROLA ii TITLE 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ...

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... STOP Mode ...........................................................................................................9-1 9.2 WAIT Mode ............................................................................................................9-1 9.3 SLOW Mode ..........................................................................................................9-3 9.4 Data-Retention Mode ............................................................................................9-3 10.1 User Mode ...........................................................................................................10-1 10.2 Self-Check Mode .................................................................................................10-1 10.3 Bootstrap Mode ...................................................................................................10-3 MC68HC05SR3 TITLE 8 9 LOW POWER MODES 10 OPERATING MODES Page Number TPG MOTOROLA iii ...

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... User Mode ............................................................................................................ A-2 A.4 Bootstrap Mode .................................................................................................... A-2 A.4.1 EPROM Programming .................................................................................... A-3 A.4.2 Program Control Register (PCR) .................................................................... A-3 A.4.3 EPROM Programming Sequence ................................................................... A-3 A.5 Mask Option Register (MOR) ............................................................................... A-4 A.6 Pin Assignments................................................................................................... A-5 MOTOROLA iv TITLE 11 ELECTRICAL SPECIFICATIONS 12 A MC68HC705SR3 Page Number TPG MC68HC05SR3 ...

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... Programming model ...............................................................................................8-1 8-2 Stacking order ........................................................................................................8-2 9-1 STOP and WAIT Mode Flowcharts.........................................................................9-2 10-1 MC68HC05SR3 Self-Check Circuit ......................................................................10-2 12-1 40-pin DIP Package..............................................................................................12-2 12-2 42-pin SDIP Package ...........................................................................................12-2 12-3 44-pin QFP Package ............................................................................................12-3 MC68HC05SR3 TITLE Page Number TPG MOTOROLA v ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA vi TPG MC68HC05SR3 ...

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... DC Electrical Characteristics for 3V Operation.....................................................11-3 11-3 ADC Electrical Characteristics for 5V and 3V Operation......................................11-4 11-4 Control Timing for 5V Operation ...........................................................................11-5 11-5 Control Timing for 3V Operation ...........................................................................11-6 A-1 MC68HC705SR3 Operating Mode Entry Conditions ............................................ A-2 MC68HC05SR3 LIST OF TABLES TITLE Page Number TPG MOTOROLA vii ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA viii TPG MC68HC05SR3 ...

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... On-chip crystal oscillator, with built-in capacitor for RC option • Second software programmable external interrupt line (IRQ2) • Direct LED drive capability on all ports • Programmable 20K pull-up resistors integrated into I/O ports MC68HC05SR3 1 GENERAL DESCRIPTION 1 TPG MOTOROLA 1-1 ...

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... The bus frequency is 16 times slower than the normal mode. Thus, the power-on reset delay will also be 16 times longer. The default setting is “Slow mode” disabled. MOTOROLA 1-2 Table 1-1 Power-On Reset Delay Mask Option Power-On Reset Delay ...

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... Figure 1-1 MC68HC05SR3/ MC68HC705SR3 Block Diagram MC68HC05SR3 KEYBOARD INTERRUPT 0 ACCUMULATOR 0 INDEX REGISTER STACK POINTER 4 0 PROGRAM COUNTER 8-Bit ADC 8-BIT COUNTER GENERAL DESCRIPTION 1 8 PA0 - PA7 8 PB0 - PB7 8 PC0 - PC7 PD7 PD6/IRQ2 PD5/V RH PD4/V RL PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0 TPG MOTOROLA 1-3 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 1-4 GENERAL DESCRIPTION TPG MC68HC05SR3 ...

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... VDD. The TIMER pin provides an optional gating input to the timer Refer to Section 6 for additional information. The OSC1 and OSC2 pins are the connections for the 11, 12 on-chip oscillator. See Section 2.2 for detail. PIN DESCRIPTIONS DESCRIPTION TPG MOTOROLA 2-1 2 ...

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... The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the following configurations are available crystal or ceramic resonator as shown in Figure 2-1(a external clock signal as shown in Figure 2-1(b options as shown in Figure 2-1(c) and Figure 2-1(d). MOTOROLA 2-2 42-pin SDIP 44-pin QFP PIN No. ...

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... OSC2 input not connected, as shown in Figure 2-1(b). MC68HC05SR3 , is divided by two to produce the internal operating OSC MCU OSC2 OSC1 25p (b) External clock source connection V DD MCU OSC2 OSC1 R (d) RC option 2 - internal resistor 25% to 50% accurate PIN DESCRIPTIONS 2 OSC2 Unconnected External Clock OSC2 TPG MOTOROLA 2-3 ...

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... Figure 2-2 and Figure 2-3 can be induced. 4.0 3.5 3.0 2.5 2.0 1.5 Figure 2-2 Typical Oscillator Frequency for Selected External Resistor 2.25 2.00 1.75 1.50 1.25 1.00 Figure 2-3 Typical Oscillator Frequency for Wire-Strap Connection MOTOROLA 2 Resistance (K ) 2.0 2.5 3.0 3.5 4.0 4.5 ...

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... PA1 8 33 PA0 PC0 9 32 PB7 PC1 10 31 PB6 PC2 11 30 PB5 PC3 12 29 PB4 PC4 13 28 PB3 PC5 14 27 PB2 PC6 15 26 PB1 PC7 16 25 PB0 PD7 17 24 PD0/AN0 18 23 PD1/AN1 19 22 PD2/AN2 20 21 PD3/AN3 PIN DESCRIPTIONS 2 TPG MOTOROLA 2-5 ...

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... VSS(EXT) MOTOROLA 2-6 VSS(INT VSS(EXT RESET 3 40 IRQ 4 39 VDD 5 38 OSC1 6 37 OSC2 7 36 VPP 8 35 TIMER 9 34 PC0 10 33 PC1 PC2 31 PC3 13 30 PC4 14 29 PC5 15 28 PC6 16 27 PC7 17 26 PD7 18 25 PD6/IRQ2 19 24 PD5/VRH PD4/VRL Figure 2-5 Pin Assignment for 42-pin SDIP ...

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... Port pin is programmed as an input, any read of the Port Data Register will return the logic state of the corresponding I/O pin. The locations of the Data Registers for Port and D are at $00, $01, $02, and $03 respectively. The Port Data Registers are unaffected by reset. MC68HC05SR3 3 Table 3-1 I/O Pin Functions I/O Pin Function INPUT/OUTPUT PORTS 3 TPG MOTOROLA 3-1 ...

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... When the ADON bit is set in the ADC Status and Control Register, PD0 to PD3 are configured as ADC inputs AN0 to AN3 respectively. PD4 and PD5 are configured as V See Section 7 for details on the Analog to Digital Converter. MOTOROLA 3-2 DATA DIRECTION REGISTER BIT ...

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... Although the ports each has high current drive capability, designs should limit the total port currents to not more than 100mA. MC68HC05SR3 All ports PB5-PB7 in low current mode typical (volts = INPUT/OUTPUT PORTS best case typical worst case best case worst case 4 5 TPG MOTOROLA 3-3 3 ...

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... MOTOROLA 3-4 V (volts worst case typical best case PB5-PB7 in low current mode worst case All ports typical best case Figure 3-3 Typical All ports PB5-PB7 in low current mode ...

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... PB5-PB7 in low current mode worst case –1 typical best case –2 –3 worst case typical –4 All ports –5 best case = bit 6 bit 5 bit 4 bit 3 PIL PDP PCP INPUT/OUTPUT PORTS 3 State bit 2 bit 1 bit 0 on reset PBP PB1 PB0 0000 0000 TPG MOTOROLA 3-5 3 ...

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... The internal 20K pull-up resistor is connected to the input of PB1. 0 (clear) – No pull-up resistor is connected to the input of PB1. PB0 — PB0 pull-up 1 (set) – The internal 20K pull-up resistor is connected to the input of PB0. 0 (clear) – No pull-up resistor is connected to the input of PB0. MOTOROLA 3-6 INPUT/OUTPUT PORTS TPG MC68HC05SR3 ...

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... On the MC68HC705SR3, this ROM is replaced by EPROM. Note: Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. MC68HC05SR3 4 MEMORY AND REGISTERS 4 TPG MOTOROLA 4-1 ...

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... User ROM/ EPROM 3840 Bytes $1EFF $1F00 Self-Check/ Bootstrap 240 Bytes $1FEF $1FF0 User Vectors 12 Bytes $1FFF Figure 4-1 MC68HC05SR3/ MC68HC705SR3 Memory Map MOTOROLA 4-2 0 Ports 8 Bytes Timer Registers 2 Bytes Port Option Register KBI Register Misc. Register EPROM Register ADC Registers ...

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... TD2 TD1 TD0 1111 1111 PR2 PR1 PR0 0100 -000 PBP PB1 PB0 --00 0000 KBE2 KBE1 KBE0 0000 0000 SM IRQ2F IRQ2E 0001 0000 ELAT PGM ---- --00 CH2 CH1 CH0 000- -000 AD2 AD1 AD0 uuuu uuuu TMR1 TMR0 RC unaffected TPG MOTOROLA 4-3 4 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 4-4 MEMORY AND REGISTERS TPG MC68HC05SR3 ...

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... When using the external reset, the RESET pin must stay low for a minimum of 1.5t RESET pin is connected to a Schmitt Trigger circuit as part of its input to improve noise immunity. MC68HC05SR3 5 internal processor bus clock cycles after the PORL period, the processor remains in the PORL RESETS AND INTERRUPTS 5 . The CYC TPG MOTOROLA 5-1 ...

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... If interrupts are not masked (CCR I-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2 shows the interrupt processing flow. MOTOROLA 5-2 ). LVR ...

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... OF STACK) Interrupt CPU Interrupt Reset RESET Software SWI External Interrupt IRQ IRQ2 Timer Overflow TIF Keyboard KBI RESETS AND INTERRUPTS 5 Vector Address Priority $1FFE-$1FFF highest $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF6-$1FF7 lowest $1FF4-$1FF5 TPG MOTOROLA 5-3 ...

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... Y 5 Figure 5-2 Hardware Interrupt Processing Flowchart MOTOROLA 5-4 From RESET Is I-bit Set IRQ External External Interrupt Interrupt ? Request Latch N Y IRQ2 External Interrupt ? N Y Timer Interrupt Keyboard Interrupt? N Fetch Next Instruction Y SWI Instruction RTI Instruction? N Execute Instruction RESETS AND INTERRUPTS ...

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... Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. MC68HC05SR3 bit 6 bit 5 bit 4 bit 3 KBIE KBIC INTO INTE LVRE RESETS AND INTERRUPTS State bit 2 bit 1 bit 0 on reset SM IRQ2F IRQ2E 0001 0000 TPG MOTOROLA 5-5 5 ...

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... INTO BIT 100K IRQ 5 IRQ Wired ORed Interrupt signals IRQ MOTOROLA 5-6 DD & & (a) Interrupt Function Diagram t ILIH t ILIL t ILIH (b) Interrupt Mode Diagram Figure 5-3 External Interrupt RESETS AND INTERRUPTS + EXTERNAL & INTERRUPT REQUEST I-BIT (CCR) POWER-ON RESET EXTERNAL RESET EXTERNAL INTERRUPT ...

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... KBIE KBIC INTO INTE LVRE bit 6 bit 5 bit 4 bit 3 TIF TIM TCEX TINE PREP RESETS AND INTERRUPTS State bit 2 bit 1 bit 0 on reset SM IRQ2F IRQ2E 0001 0000 State bit 2 bit 1 bit 0 on reset PR2 PR1 PR0 0100 -100 TPG MOTOROLA 5-7 5 ...

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... The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the contents in $1FF4-$1FF5. KBEx of KBIM & KBIE bit of MCR ($0C bit 7) DDR0-DDR7 Internal Data bit (0-7), Port A MOTOROLA 5 & 20K & Pad Logic Figure 5-4 Keyboard Interrupt Circuitry ...

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... KBIE KBIC INTO INTE LVRE bit 6 bit 5 bit 4 bit 3 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 0000 0000 RESETS AND INTERRUPTS State bit 2 bit 1 bit 0 on reset SM IRQ2F IRQ2E 0001 0000 State bit 2 bit 1 bit 0 on reset TPG MOTOROLA 5-9 5 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 5-10 RESETS AND INTERRUPTS TPG MC68HC05SR3 ...

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... PRER bit in the TCR. This will allow for truncation-free counting. The input clock for the timer sub-system is selectable from internal, external combination of internal and external sources. The TCEX and TINE bits in the Timer Control Register selects the timer input clock. MC68HC05SR3 6 TIMER TIMER 6 TPG MOTOROLA 6-1 ...

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... MOTOROLA 6-2 Timer Data Register ($08) 8 8-bit count-down timer counter 7-bit prescaler counter RST 8 Prescaler Overflow Detect ( MUX) Circuit Interrupt Circuit 8 TIF TIM TCEX TINE PRER PR2 Timer Control Register ($09) Clock Source Logic TCEX TINE Clock Source 0 0 Internal clock to timer ...

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... TCEX TINE PRER PRE2 PRE1 Clock Source Internal clock to timer “AND” of internal clock and TIMER pin to timer Input clock to timer disabled TIMER pin to timer TIMER State bit 0 on reset PRE0 0100 -100 6 TPG MOTOROLA 6-3 ...

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... TIM bit prior entering STOP mode. After exiting STOP mode TIF bit can then be cleared. The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. MOTOROLA 6-4 PR2 ...

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... Figure 7-1 ADC Converter Block Diagram MC68HC05SR3 ANALOG TO DIGITAL CONVERTER 7 8-bit capacitive DAC with sample and hold Successive approximation register and control Result 8 ADC Status and Control Register ($0E) CH0 CH1 CH2 ADC Data Register ($0F) 7 VRH VRL ADON ADRC COCO TPG MOTOROLA 7-1 ...

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... At power-on or external reset, both the ADRC and ADON bits are cleared, thus the ADC is disabled. MOTOROLA 7-2 +V )/2. Selection is done via the CHx bits in the ADC Status and ...

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... RH RL for internal reference points. Table 7-1 shows the signals selected by the channel select bits. MC68HC05SR3 ANALOG TO DIGITAL CONVERTER bit 5 bit 4 bit 3 bit 2 bit 1 CH2 CH1 ADON State bit 0 on reset CH0 000- -000 7 for the current sources to TPG MOTOROLA 7-3 ...

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... ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the ADC is in use and the internal bus clock is above 1MHz recommended that the ADRC bit be cleared. In STOP mode, the ADC stops operation. MOTOROLA 7-4 Table 7-1 ADC Channel Assignments CH0 ...

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... The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. MC68HC05SR3 CPU CORE AND INSTRUCTION SET Accumulator 7 0 Index register 7 0 Program counter 7 0 Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry 8 TPG MOTOROLA 8-1 ...

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... Each bit is explained in the following paragraphs. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. MOTOROLA 8-2 7 Condition code register ...

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... This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 8-1. MC68HC05SR3 CPU CORE AND INSTRUCTION SET 8 TPG MOTOROLA 8-3 ...

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... Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 8-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 8-8). MOTOROLA 8-4 CPU CORE AND INSTRUCTION SET ...

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... H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Addressing mode Cycles Bytes Inherent 11 1 Addressing modes Immediate Direct Extended Opcode $42 Indexed Indexed Indexed (no (8-bit (16-bit offset) offset) offset TPG MOTOROLA 8-5 8 ...

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... Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high 8 Branch to subroutine Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n MOTOROLA 8-6 Table 8-3 Branch instructions Function Mnemonic BRA BRN BHI BLS BCC ...

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... CPU CORE AND INSTRUCTION SET Addressing modes Inherent Inherent Direct (A) ( Table 8-6 Control instructions Inherent addressing mode Mnemonic Opcode # Bytes # Cycles TAX 97 TXA 9F SEC 99 CLC 98 SEI 9B CLI 9A SWI 83 RTS 81 RTI 80 RSP 9C NOP 9D STOP 8E WAIT 8F Indexed Indexed (no (8-bit offset) offset TPG MOTOROLA 8-7 8 ...

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... BSR CLC CLI CLR CMP Address mode abbreviations BSC Bit set/clear BTB Bit test & branch DIR Direct EXT Extended INH Inherent MOTOROLA 8-8 Table 8-7 Instruction set Addressing modes IMM DIR EXT REL IX IX1 IMM Immediate H Half carry (from bit 3) ...

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... Tested and set if true, cleared otherwise • Not affected ? Load CCR from stack 0 Cleared 1 Set TPG MOTOROLA 8-9 ...

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... MOTOROLA 8-10 Table 8-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05SR3 ...

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... Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. Address bus high MC68HC05SR3 CPU CORE AND INSTRUCTION SET HMOS/M146805 CMOS EA = PC+ (PC+1); PC PC+2 0; Address bus low (PC+1) Family Microcomputer/ 8 TPG MOTOROLA 8-11 ...

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... This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. ...

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... Otherwise, control proceeds to the next instruction. The span of relative addressing is from –126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ...

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... THIS PAGE LEFT BLANK INTENTIONALLY 8 MOTOROLA 8-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05SR3 ...

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... Timer pin, on the occurrence of external events. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can “wake” the MCU. All other registers, memory, and input/output lines remain in their previous states. MC68HC05SR3 9 LOW POWER MODES 9 TPG MOTOROLA 9-1 ...

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... STOP Stop External Oscillator, Stop Internal Timer Clock, and Reset Start-Up Delay Stop Internal Processor Clock, Clear I-Bit in CCR External RESET External Hardware Interrupt? 9 MOTOROLA 9 Reset External Oscillator, and Stabilization Delay End of Start-Up N Delay? Y Restart Internal Processor Clock Fetch Reset Vector ...

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... INTO INTE LVRE = bit 6 bit 5 bit 4 bit 3 KBIE KBIC INTO INTE LVRE LOW POWER MODES State bit 2 bit 1 bit 0 on reset SM IRQ2F IRQ2E 0001 0000 32. OSC =f 2. OSC State bit 2 bit 1 bit 0 on reset SM IRQ2F IRQ2E 0001 0000 TPG MOTOROLA 9-3 9 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY 9 MOTOROLA 9-4 LOW POWER MODES TPG MC68HC05SR3 ...

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... Table 10-2 lists the LEDs’ on-off patterns and their corresponding indications. MC68HC05SR3 10 Table 10-1 Mode Selection PB1 SELF-CHECK/ BOOTSTRAP TST DD and PB1 pins are between V PP pin and PB1 pin TST DD OPERATING MODES MODE USER and Once in the DD TPG MOTOROLA 10-1 ...

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... RESET + 1 F +5V 330 330 10 330 330 MOTOROLA 10-2 MC68HC05SR3 4MHz OSC1 OUT OSC2 Crystal OSC RESET +5V 10K PB0 D1 PB4 PB1 D2 PB5 PB2 D3 PB6 PB3 D4 PB7 Figure 10-1 MC68HC05SR3 Self-Check Circuit OPERATING MODES PA0 PA1 PA2 PA3 PA4 PA5 PA6 ...

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... Table 10-2 Self-Check Report D2 D1 REMARKS O.K. (self-check is on-going Bad port Bad port Bad port Bad port Bad RAM 1 0 Bad ROM 0 0 Bad SWI 1 1 Bad IRQ ( and PB1 pin TST DD OPERATING MODES . Once in the bootstrap DD 10 TPG MOTOROLA 10-3 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY 10 MOTOROLA 10-4 OPERATING MODES TPG MC68HC05SR3 ...

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... 11.2 Thermal Characteristics CHARACTERISTICS Thermal resistance DIP SOIC QFP MC68HC05SR3 ELECTRICAL SPECIFICATIONS 11 SYMBOL V –0 –0 –0.3 to 2xV IN SS and –40 to +85 T –65 to +150 STG SYMBOL VALUE VALUE UNIT out DD UNIT C/W C/W C/W TPG MOTOROLA 11-1 11 ...

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... Wait, Stop I : All ports configured as inputs (5) Run (operating Wait I DD from rail loads, less than 50pF on all outputs, C (6) Stop I measured with OSC1=V DD (7) Wait I is affected linearly by the OSC2 capacitance. DD MOTOROLA 11-2 =0Vdc, temperature range SYMBOL MINIMUM =–0.8mA) LOAD ...

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... I DD — — — — — — I — — — — — — OUT C — — 100 =0.2Vdc –0.2Vdc =2.0MHz), all inputs 0.2Vdc OSC =20pF on OSC2. L MAXIMUM UNIT — V 0.1 V — V 0 5.2 — 0 3 176 K TPG MOTOROLA 11-3 ...

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... Error includes quantization. ADC accuracy may decrease proportionately as V (2) Source impedances greater than 10K adversely affect internal RC charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. 11 MOTOROLA 11-4 PARAMETER Number of bits resolved by the ADC ...

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... MHz 0.1 4.0 MHz dc 4.0 MHz — 2.0 MHz — 2.0 MHz dc 2.0 MHz 500 — ns — — 100 ms — 100 ms 1.5 — t CYC — t CYC 125 — ns — t CYC 125 — ns — t CYC 90 — ns – – TPG MOTOROLA 11-5 11 ...

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... DD (2) The TIMER input pin is the limiting factor in determining timer resolution. (3) The minimum period t service routine plus 19 t (4) Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C). 11 MOTOROLA 11-6 Table 11-5 Control Timing for 3V Operation =0Vdc, temperature range SYMBOL ...

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... MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 40-pin DIP, 42-pin SDIP and 44-pin QFP packages for the MC68HC05SR3. MC68HC05SR3 MECHANICAL SPECIFICATIONS 12 12 TPG MOTOROLA 12-1 ...

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... DIP Package (Case 711-03 12.2 42-Pin SDIP Package (Case 858-01 MOTOROLA 12 Figure 12-1 40-pin DIP Package 22 - Figure 12-2 42-pin SDIP Package MECHANICAL SPECIFICATIONS MC68HC05SR3 TPG ...

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... QFP Package (Case 824A-01 -A- L DETAIL - - - DETAIL C Figure 12-3 44-pin QFP Package MC68HC05SR3 MECHANICAL SPECIFICATIONS DETAIL C - -A,B,D- B DETAIL A F BASE METAL SECTION B–B 12 TPG MOTOROLA 12-3 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY 12 MOTOROLA 12-4 MECHANICAL SPECIFICATIONS TPG MC68HC05SR3 ...

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... Functionally equivalent to MC68HC05SR3 • 3840 bytes of user EPROM • EPROM bootstrap mode replaces Self-Check mode on the MC68HC05SR3 • Available in the following packages: OTP 40-pin PDIP, windowed EPROM 40-pin Ceramic DIP, OTP 42-pin SDIP, and 44-pin QFP MC68HC05SR3 A MC68HC705SR3 A TPG MOTOROLA A-1 ...

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... This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootstrap function does not have to be done from an external EPROM, but it may be done from a host. A The user code must be a one-to-one correspondence with the internal EPROM addresses. MOTOROLA A-2 V PB1 PP ...

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... A.4.1 EPROM Programming Programming boards are available from Motorola for programming the on-chip EPROM. Please contact your Motorola Representative. The Programming Control register (PCR) is provided for EPROM programming. The function of the EPROM depends on the device operating mode. A.4.2 Program Control Register (PCR) ...

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... When programmed to “1”, this bit disables some functions of the Bootstrap mode, preventing external reading of EPROM content. TMR2:TMR0 — Power-on Reset Delay The amount Power-On Reset delay is set by programming these three bits. The delay is selected as follows: A MOTOROLA A-4 ;reset PCR ;load index register with 00 ;set ELAT bit ;load data= ...

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... RC — Crystal Oscillator Option 1 (set) – Resistor option selected. 0 (clear) – Crystal option selected. A.6 Pin Assignments See Section 2.3 for pin assignments for the available packages. MC68HC05SR3 MC68HC705SR3 A TPG MOTOROLA A-5 ...

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... THIS PAGE LEFT BLANK INTENTIONALLY A MOTOROLA A-6 MC68HC705SR3 TPG MC68HC05SR3 ...

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GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TIMER MC68HC705SR3 TPG ...

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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS ...

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... USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 !MOTOROLA MC68HC05SR3D/H ...

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