LH28F008SCT-12 Sharp, LH28F008SCT-12 Datasheet
LH28F008SCT-12
Related parts for LH28F008SCT-12
LH28F008SCT-12 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F008SCT-L12 Flash Memory Issue Date: May 7, 1999 ® 8M (1M ×8) (Model No.: LHF08CH3) Spec No.: EL104164B Integrated Circuits Group ...
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... SHARP l Handle this document copyright law. Any reproduction, express written permission l When using the products covered and the precautions outlined in the following be liable for any damages precautions. (1) The products covered application areas. When using the products covered in Paragraph (2), even for the following ...
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SHARI= 1.0 INTRODUCTION ................................................... .................................................... 1.1 New Features.. ................................................ 1.2 Product Overview 2.0 PRINCIPLES OF OPERATION.. 2.1 Data Protection ................................................... 3.0 BUS OPERATION ................................................. 3.1 Read ................................................................... 3.2 Output Disable .................................................... 3.3 Standby ............................................................... 3.4 Deep Power-Down .............................................. 3.5 Read ...
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... Its enhanced suspend capabilities secure code storage applications, such as networking, downloaded to DRAM, the LH28F008SCT-L12 ZND, selective hardware block locking, Jltimate control of their code security The LH28F008SCT-L12 is manufactured ndustry-standard package: ...
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... The V,, transitions to GND is recommended that switch V,, off during read operation. *To take advantage of SmartVoltage allow V,, connection to 3.3V or 5V. 1.2 Product Overview The LH28F008SCT-L12 is a high-performance SmartVoltage Flash memory organized 3 bits. The IM-byte of data is arranged SK-byte blocks which are individually ockable, and unlockable in-system ...
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Individual block locking uses a combination sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master Jates block lock-bit modification. zonfiguration operations (Set Block and Clear ...
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... SHARP 49 Ale A17 A16 AIS A14 An A12 CE# vcc VPP RP# 41 Alo LHF08CH3 Figure 1. Block Diagram 40-LEAD TSOP STANDARD PINOUT 1 Omm x 20mm TOP VIEW Figure 2. TSOP 40-Lead Pinout WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQI DQo Rev ...
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... SHARP Type Symbol ADDRESS INPUT A,-Al 9 are internally latched during a write cycle. DATA INPUT/OUTPUTS: INPUT/ data during memory array, status register, and identifier code read cycles. Data pins float DQo-DQ7 OUTPUT to high-impedance latched during a write cycle. CHIP ENABLE: CE# INPUT amplifiers. levels. ...
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... SHARP 2 PRINCIPLES OF OPERATION The LH28F008SCT-L12 SmartVoltage includes an on-chip WSM to manage byte write, and lock-bit configuration allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor RAM-Like interface timings. After initial device ...
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... DC+,-DQ, are occurs with initialization may not occur because the flash memory may be providing data. SHARP’s initialization following the device in of the RP# input. In this application, reduces device by the same RESET# are placed in CPU. ...
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Read Identifier Codes Operation The read identifier codes operation device code, manufacturer code, configuration codes for each block, and the master lock configuration code (see Figure manufacturer and device codes, the system CPU can automatically match the device algorithms. ...
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SHARI= Notes Mode 1,2,3,8 Read 3 Output Disable Standby 3 Deep Power-Down 4 Read Identifier Codes 8 Write 3,6,7,8 ‘4OTES: When Vpp<VppLK, memory contents I. Refer to DC Characteristics can be VI, or VrH for control pins and ...
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... WSM as the byte write setup. to set a block lock-bit. RP# must be at V,, to clear block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits by SHARP for future device implementations Second Bus Cycle 1 Addr12) 1 Datat3) Oper(‘) ...
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Read Array Command Upon initial device power-up and after exit from deep Dower-down mode, the device defaults to read array node. This operation is also initiated by writing Read Array command. The device remains ‘or reads until another command ...
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When the block erase is complete, status register SR.5 should be checked block detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command ...
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... SHARP 4.8 Byte Write Suspend Command The Byte Write Suspend command interruption to read data in other locations. Once the byte write process the Byte Write Suspend command WSM suspend the byte write predetermined point in the algorithm. continues to output status register after the Byte Write ...
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Clear Block Lock-Bits Command i All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared only the Clear Block Lock-Bits command. master lock-bit is ...
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WSMS 1 ESS 1 ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND ...
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SHARI= * Read Status FULLSTATUSCHECKPROCEDURE Figure LHFOSCH3 Bus Command Operation I I write Erase Setup Ems.3 write COtlfilll7 Read 1.,, Repeat for subsequent block erasures. Full status check can be done after each block erase or alter a sequence block ...
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SHARI= Data and Address FULL STATUS CHECK PROCEDURE Read Status Aeglster Data(See Above) Deuce Protect Error Byte Write Successful Figure 6. Automated LHFOSCH3 Command Setup Byte Wnte write write Byte Wnte Read Suspend Byte Standby Repeat for subsequent byte writes. ...
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... SHARP Byte write Loop Figure LHF08CH3 Bus Command Operation Standby Standby Write 7. Block Erase Suspend/Resume Flowchart Comments Data=BOH Addr=X Status Regtster Data Addr=X Check SR.7 l=WSM Ready O=WSM Busy Check SR.6 l=Block Erase Suspended O&lock Erase Completed Data=DOH Addr=X Rev.1.0 ...
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SR. Byte Write Completed SR. Figure 8. Byte Write Suspend/Resume LHF08CH3 Bus Command 0per&l0ll Byte Write Data&OH write Suspend Addr=X Status Register Read Addr=X I---- Check l=WSM Standby o=WSM Check SR.2 t=Byte Write Suspended ...
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Block/Dewce Address Block/Device Address f Read Status Register 1::3 0 SR.7= 1 Check if Desired PULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Figure 9. Set Block LHF08CH3 T BUS Command Operation Data&OH set Addr=Blcck Write Block/Master Dewce Lock-Bit ...
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... SHARP FULL STATUS CHECK PROCEDURE Device Protect Error Command Sequence Error Clear Block Lock-Bits Error Figure LHF08CH3 Bus Command Operation Clear Block Write Lock-Bits Setup Clear Block write Lock-Bits Confirm Read Standby Write FFH after the Clear Block Lock-Bits place device I” ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. control SHARP provides three accommodate multiple memory Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention not occur. To use these control ...
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SI-IARP 5.5 Vcc, Vpp, RP# Transitions Block erase, byte write and lock-bit configuration not guaranteed if V,, falls outside of a valid VPPH,,z3 range, V,, falls outside of a valid Vcc,,s RP##V,H or V,,. If V,, error is detected, register ...
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SI-IARP 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration . . . . . . . . . . . 0°C to +70X(‘) Temperature under Bias . . . . ...
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... SHARP 2.2 AC INPUT/OUTPUT TEST CONDITIONS ~~~~~~)(~ AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0.” Input timing input rise and fall times (10% Figure 11. Transient ~~~~iqzq(~ AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic “0.” Input timing ...
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... SHARP i.2.3 DC CHARACTERISTICS Notes Sym. Parameter Input Load Current ‘LI Output Leakage Curreni t ‘LO V,, Standby Current ‘cc, h&Dnep Power-Down ‘CCD 1 V,, Read Current 1,5,6 ‘cc, \ J,, Byte Write or ccw : jet Lock-Bit Current -F \ 1,7 J,, Block Erase or CCE ( Zlear Block Lock-Bits ( hrrent \ J,, Byte Write or Block ...
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... SHARP Notes Sym. Parameter Input Low Voltage 7 V,, 7 Input High Voltage VI, Output Low Voltage 3,7 VOL VoH, Output High Voltage 3,7 VW VOH2 Output High Voltage 3,7 (CMOS) V,,,, V,, Lockout during 497 Normal Operations V,,,,, V,, during Byte Write, Block Erase or Lock-Bit Operations ...
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AC CHARACTERISTICS - READ-ONLY Versiond4) Sym. 1 Parameter 1 Read Cycle Time See 5.OV V,, Read-Only Operations Versiond4) Sym. 1 Parameter t*“n” Read Cycle Time tA”n” Address to Output Delay fF, 0” CE# to Output Delay tpH()” RP# High ...
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SHARI= NOTES: 1. See AC Input/Output Reference Waveform 2. OE# may be delayed ELQv-bLQv after the falling edge of CE# without 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational LHF08CH3 for ...
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SliARP 4- VIH CE#(E) VIL VIH OE#(G) VIL VIH WE#(W) VIL VOH DATA( D/Q) (DQo-DQ7) VOL vcc tPHQV VIH t RP#(P) VIL Figure 15. AC Waveform LHF08CH3 Device Data Valid . ..I..#... Address Stable tAVAV ,,,,.,..I. . ..#...I.. “““““7 for ...
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AC CHARACTERISTICS - WRITE OPERATION(‘) Version&) _ __-.-_.- Parameter Sym. 1 :ovety to WE# Going Low NOTE: See 5.OV V,, WE#-Controlled Writes for notes 1 through 5. Versions@) Parameter Sym. 1 NOTE: See 5V V,, AC Characteristics - Write ...
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SliARI= Versiat@) __._. -.._ Sym. ( Parameter tAvnv ( Write Cycle Time NOTES: 1. Read timing characteristics during block erase, byte write and lock-bit configuration Refer to AC Characteri! sties for read-only during read-onry operations. 2. Sampled, not 100% tested. ...
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SHARI= VIH ADDRESSES(A) VIL VIH CE#(E) VIL VIH OH(G) DATA(D/Q) RY/BY#(R) VHH RP#(P) VIH NOTES: 1. Vcc power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address 4. Automated erase or ...
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ALTERNATIVE CE#-CONTROLLED I c VetGods) -~ _.-.~- I Sm. I Parameter Write Cycle Time tA”*” tpHF, RP# High Recovery to CE# Going Low t WE# Setuo to CE# Goina Low CE# Going High ‘ram CE# High ...
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... SHARP _ -_-_ -._- VersiansW Sym. 1 Parameter Write Cycle Time RP# High Recovery to CE# Going Low tpHF, tw, I-, WE# Setup to CE# Going Low tr, pc( CE# Pulse Width hFH RP# V,,,, Setup to CE# Going High t”pFH VP,, Setup to CE# Go ing High fl\“F, I Address Setup to CE# Going , tn”FH Data Setup to CE# Going Hig ...
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VIH ADDRESSES(A) VIH WE#(W) VIH OE#(G) CE#(E) DATA(D/Q) VHH RP#(P) VIH NOTES: 1. Vcc power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address 4. Automated erase or program delay. ...
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... SHARP 6.2.7 RESET OPERATIONS “IJH ~~ RY/BY#( R) VOL VIH RP#(P) VIL VOH RY/BY#(R) VOL VIH RP#(P) VIL (B)Reset 2.7Vl3.3Vl5V vcc VIL VIH RP#(P) VIL Figure Sym. tPLPH tPLRH t235VPH I ‘JOTES RP# is asserted while a block erase, byte write, or lock-bit configuration will complete within 1 OOns. ...
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BLOCK ERASE, BYTE WRITE AND LOCK-BIT t WHQVs Set Lock-Bit Time tFHn”2 t WHQV4 Clear Block Lock-Bits Time fFH()“4 twHRH1 Byte Write Suspend Latency Time to ~ Read iwHRH2 Erase Suspend Latency Time to Read FHRH7 ‘4OTES: I. Typical ...
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... ADDITIONAL INFORMATION 7.1 Ordering Information Product line designator for all SHARP Flash products ~L~H/2181F10~0~8/SIC~(H~T/ Device Density 008 = B-Mbit Architecture S = Regular Block Power Supply Type C = SmartVoltage Technology Operating Temperature] Blank = 0°C - +7O” -40°C - +85”C Option Order Code 1 L!-l28F008SCT-L12 LHF08CH3 -IL/l ...
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... Inner case Card board _______-.-.....-____..---~--~~.......~-~~.~.------~.~~~---.------~--.--~.---..-....................~.... _......._.__......__~.~~~~.~~..~~~~~.....~~~~~....~...~ Label Paper Outer case Card board (Devices shall be placed into LHFOSCH3 ) 10 5 LH28F008SCT-L 12 SHARP ww xxx Indicates the product (01,02,03 52,53) - Denotes the product ion year. (Lower two digit - Denotes the product ion ref.code (No marking ...
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... SHARP 3-2. Outline dimension of tray Refer to attached drawing Storage and Opening of Dry Packing 4. 4-l. Store under conditions (1) Temperature range (2) Humidity Notes on opening the dry packing (1) Before opening the dry packing, prepare a working table which is grounded against ESD and use a grounding strap. ...
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... SHARP LH28FOO8SCT-L12 ISEE DETAIL A ____ :cEz : UJ APAN ~~&&%6$$&0?--3{~& NOTES : Marking specification when “JAPAN" is marked. ml r;‘lkk. NAME : TSOP40-P-1020 LEAD FINISH i PLATING NOTE Plastic @(iL UNIT DRAWING NO. j AA1105 LHF08CH3 DETAIL A \ TIN-LEAC .$%% -95X$7 3~~s~-9fi#?rir;l~, body dimensions do not include burr of resin. ...
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StiARl= i 18. 4+0. 2 /SEE DETAIL A p&- ANfl ~%WZ?t%j@~-?- NOTES : Marking specification when “JAPAN” is not marked. lAME [ TSOP40-P-1020 LEAD FINISH ; PLATING NOTE Plastic g-I2 / DRAWING NO. i AA1105 UNIT ...
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... SHARP . $33 1 iAME;TSOP40-lOZOTCM-RH stiz DRAWING NO. 1 CV644 UNIT ! LHF08CH3 tic% NOTE ...
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... Reflow soldering conditions Measurement point Storage conditions Note Recommended Reflow LHF08CH3 LHF08CH3 conditions for two time reflow LH28F008SCT-L12(TS0P40-P-1020) Tray (Dry packing) Reflow soldering (Air) Peak temperature of 230°C or less. 200°C or over, duration of less Preheat temperature of 1‘25-150”C,duration than 180 seconds. ...
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... SHARP Flash memory LHFXXCXX family Data Protection Noises having a level exceeding the limit generated under specific operating conditions on some systems. Such noises, when induced onto WEB signal or power supply, may be interpreted commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, ...