LH28F320BJHE-PBTL90 Sharp, LH28F320BJHE-PBTL90 Datasheet
LH28F320BJHE-PBTL90
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LH28F320BJHE-PBTL90 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F320BJHE-PBTL90 ® Flash Memory 32M (2M x 16/4M × 8) (Model No.: LHF32J08) Spec No.: EL12X044 Issue Date: October 16, 2000 Integrated Circuits Group ...
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... Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs ...
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... INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 8 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 9 3.1 Read.............................................................................. 9 3.2 Output Disable.............................................................. 9 3.3 Standby......................................................................... 9 3.4 Reset............................................................................. 9 3.5 Read Identifier Codes................................................. 10 3.6 OTP(One Time Program) Block ................................ 10 3 ...
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... Bottom Boot Location ■ Extended Cycling Capability Minimum 100,000 Block Erase Cycles SHARP’s LH28F320BJHE-PBTL90 Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F320BJHE-PBTL90 can operate at V capability realize battery life and suits for cellular phone application. ...
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... GND is recommended for designs that switch V off during read operation. CCW 1.2 Product Overview The LH28F320BJHE-PBTL90 is a high-performance 32M-bit Boot Block Flash memory organized as 2M-word of 16 bits or 4M-byte of 8 bits. The 2M-word/4M-byte of data is arranged in two 4K-word/8K-byte boot blocks, six 4K-word/8K-byte parameter blocks and sixty-three 32K- word/64K-byte main blocks which are individually erasable, lockable and unlockable in-system ...
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... For example, changing data from "10111101" to "10111100" requires "11111110" programming. LHF32J08 1.3 Product Description supply CC 1.3.1 Package Pinout LH28F320BJHE-PBTL90 Boot Block Flash memory is available in 48-lead TSOP package (see Figure 2). CCR 1.3.2 Block Organization , the I CMOS CC This product architecture providing system memory integration ...
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... Input A -A Decoder -1 20 Buffer Address Decoder Latch Address Counter WE# RP CCW WP# 14 RY/BY LHF32J08 DQ - Output Input Buffer Buffer Identifier Register Status Register Data Comparator Y Y-Gating 32K-Word X (64K-Byte) Main Blocks ×63 Figure 1. Block Diagram 48-LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW Figure 2 ...
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... Symbol Type ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle INPUT A : Lower address input while BYTE Main Block Address Boot and Parameter Block Address DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles ...
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... Main Block 0F8000 0F7FFF 32KW/64KB Main Block 0F0000 0EFFFF 32KW/64KB Main Block 0E8000 0E7FFF 32KW/64KB Main Block 0E0000 0DFFFF 32KW/64KB Main Block 0D8000 0D7FFF 32KW/64KB Main Block 0D0000 0CFFFF 32KW/64KB Main Block 0C8000 0C7FFF 32KW/64KB Main Block 0C0000 ...
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... PRINCIPLES OF OPERATION The LH28F320BJHE-PBTL90 flash memory includes an on-chip WSM to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. It allows for: fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings ...
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... If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this ...
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... The OTP block is a special block that can not be erased. The block is divided into two parts. One is a factory program area where a unique number can be written according to customer requirements in SHARP factory. This factory program area is "READ ONLY" (Already locked). The other is a customer program area that can be used by customers ...
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... Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When the CUI additionally controls block CCW CCWH1/2 erase, full chip erase, word/byte write and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased ...
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... If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done. 9. Once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. ...
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... Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has ...
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... Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH/FFH) ...
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... Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm ...
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... Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command ...
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... OTP Program Command OTP program is executed by a two-cycle command sequence. OTP program command(C0H) is written, followed by a second write cycle that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the OTP program and program verify algorithms internally ...
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... WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS (ECBLBS Error in Block Erase, Full Chip Erase or Clear Block Lock-Bits ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range Error SR.3= ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range Error SR.3= CCW 0 1 Device Protect Error SR ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word/Byte Data and Address Read Status Register No Suspend 0 SR.7= Word/Byte Write 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error ...
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... Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Word/Byte Write Read Word/Byte Write ? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 9. Block Erase Suspend/Resume Flowchart LHF32J08 Bus Command Operation Erase ...
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... Start Write B0H Read Status Register 0 SR. Word/Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 10. Word/Byte Write Suspend/Resume Flowchart LHF32J08 Bus Command Operation Data=B0H Word/Byte Write ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error CCW 0 1 Device Protect Error SR ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error CCW 0 1 SR.1= Device Protect Error ...
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... Start Write 70H Read Status Register 0 SR.7= 1 Write C0H Write Data and Address Read Status Register 0 SR.7= 1 Full Status Check if Desired OTP Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error CCW 0 1 SR.1= Device Protect Error ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur ...
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... Power-Up/Down Protection The device is designed to offer protection against accidental block erase, full chip erase, word/byte write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power supply ( powers-up first. Internal circuitry CCW CC resets the CUI to read array mode at power-up. ...
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... ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration .............-40°C to +85°C Storage Temperature During under Bias ............................... -40°C to +85°C During non Bias ................................ -65°C to +125°C Voltage On Any Pin ...
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... AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns. Figure 14. Transient Input/Output Reference Waveform for V 1 ...
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... DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current CCR Word/Byte Write or Set Lock- CCW CC Bit Current I V Block Erase, Full Chip Erase or CCE CC Clear Block Lock-Bits Current ...
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... Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Lockout during Normal CCWLK CCW Operations V V during Block Erase, Full Chip CCWH1 CCW Erase, Word/Byte Write or Lock-Bit Configuration Operations V V during Block Erase, Full Chip ...
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... AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in Low Z ELQX t CE# High to Output in High Z EHQZ t OE# to Output in Low Z GLQX ...
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... Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V IH RP#( Figure 16. AC Waveform for Read Operations LHF32J08 Device Data Valid Address Stable t AVAV t GLQV t ELQV t GLQX t ELQX Valid Output t AVQV 34 t EHQZ t GHQZ t OH HIGH Z Rev. 1.27 ...
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... Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) (DQ - LHF32J08 Device Data Valid Address Stable t AVAV t ELQV t AVQV t GLQV t FVQV t t GLQX ELFV Data Output t ELQX t FLQZ Data Output Figure 17. BYTE# timing Waveform 35 t EHQZ t GHQZ t OH Valid ...
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... AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to WE# Going High SHWH Setup to WE# Going High VPWH CCW t Address Setup to WE# Going High ...
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... V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0" WP#( RP#( CCWH1 (V) CCW CCWLK V IL NOTES power-up and standby Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. ...
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... ALTERNATIVE CE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going High SHEH Setup to CE# Going High VPEH CCW t Address Setup to CE# Going High ...
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... V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0" WP#( RP#( CCWH1 (V) CCW CCWLK V IL NOTES power-up and standby Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. ...
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... RESET OPERATIONS High Z ("1") RY/BY#(R) (SR. ("0" RP#( High Z ("1") RY/BY#(R) (SR. ("0" RP#( (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration 2. RP#( Sym. Parameter t RP# Pulse Low Time PLPH RP# Low to Reset during Block Erase, Full Chip Erase, ...
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... BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t Word Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Byte Write Time 64K byte Block 8K byte Block Block Write Time 32K word Block (In word mode) ...
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... Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. ...