LH28F320S3TD-L10 Sharp, LH28F320S3TD-L10 Datasheet
LH28F320S3TD-L10
Related parts for LH28F320S3TD-L10
LH28F320S3TD-L10 Summary of contents
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... V selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. LH28F320S3TD-L10 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable ...
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... PIN CONNECTIONS 56-PIN TSOP (Type RP GND (TSOP056-P-1420 LH28F320S3TD-L10 TOP VIEW WP# 56 WE# 55 OE# 54 STS GND GND BYTE ...
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... BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - INPUT BUFFER QUERY ROM IDENTIFIER REGISTER COMMAND STATUS USER REGISTER INTERFACE MULTIPLEXER DATA COMPARATOR Y GATING WRITE STATE MACHINE 32 64 k-BYTE BLOCKS - 3 - LH28F320S3TD-L10 I/O CC LOGIC BYTE WE# OE# RP# WP# STS V PP PROGRAM/ERASE VOLTAGE SWITCH V CC GND ...
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... All data are then input or output IL , and DQ float. BYTE# V places the device in x16 mode, and turns off the 0-7 8-15 IH ≤ PPLK - 4 - LH28F320S3TD-L10 # and must not be low at the same time RP# inhibits IL , locked blocks can not IL , memory contents cannot be altered. Block down to GND and then ramp CC ≤ ...
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... Section 6 covers electrical specifications. The LH28F320S3TD-L10 flash memory documentation also includes ordering information which is referenced in Section 7. 1.1 Product Overview The LH28F320S3TD-L10 is a high-performance 32 M-bit Smart 3 Dual Work flash memory organized x8 2-Bank. The data is arranged in sixty-four 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system ...
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... A reset time (t CC RP# switching high until outputs are valid. Likewise, the device has a wake time (t until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared LH28F320S3TD-L10 # and RP# pins CMOS standby mode is CC ...
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... Block 8 080000 07FFFF 7 64 k-Byte Block 070000 06FFFF 64 k-Byte Block 6 060000 05FFFF 64 k-Byte Block 5 050000 04FFFF 64 k-Byte Block 4 040000 03FFFF 64 k-Byte Block 3 030000 02FFFF 64 k-Byte Block 2 020000 01FFFF 64 k-Byte Block 1 010000 00FFFF 64 k-Byte Block 0 000000 (BE Fig. 1 Memory Map - 7 - LH28F320S3TD-L10 Bank1 # = "L" ...
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... PRINCIPLES OF OPERATION The LH28F320S3TD-L10 Smart 3 Dual Work flash memory includes an on-chip WSM to manage block erase, bank erase, (multi) word/byte write and block lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erase, bank erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-like interface timings ...
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... SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU LH28F320S3TD-L10 initiates the deep power-down mode. is required PHQV is required PHWL ) before another ...
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... When CC1/2 additionally controls block erase, bank erase, (multi) -DQ ) only. word/byte write and block lock-bit configuration LH28F320S3TD-L10 Reserved for Future Implementation Block 31 Status Code Reserved for Future Implementation Block 31 (Blocks 2 through 30) Reserved for Future Implementation Block 1 Status Code Reserved for ...
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... V V CC1/2 8. Refer to Table 3 for valid D 9. Don’t use the timing both OE# and WE# are V 10. Impossible to perform simultaneous read from both banks at a time. Both BE be low at the same time LH28F320S3TD-L10 voltage V , read operations from PP PPLK on V PPH1/2 ...
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... PPH1/2/3 reliably executed when V V CC1/2 8. Refer to Table 3 for valid D 9. Don’t use the timing both OE# and WE# are V 10. Impossible to perform simultaneous read from both banks at a time. Both BE be low at the same time LH28F320S3TD-L10 IL) WE# ADDRESS 0 ...
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... Following the Third Bus Cycle, inputs the write address and write data of "N" times. Finally, input the confirm command "D0H". 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used LH28F320S3TD-L10 SECOND BUS CYCLE (NOTE 3) (NOTE 1) (NOTE 2) Data Oper ...
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... Clear Status Register command. These bits indicate various failure conditions (see Table 13.1 allowing system software to reset these bits, several operations (such as cumulatively erasing locking multiple blocks or writing several bytes LH28F320S3TD-L10 # (Either #), whichever (Either before further reads (Either 0 1 ...
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... Table 6 Query Block Status Register DESCRIPTION Block Status Register bit0 Block Lock Configuration 0 = Block is unlocked 1 = Block is locked bit1 Block Erase Status 0 = Last erase operation completed successfully 1 = Last erase operation not completed successfully bit2-7 Reserved for future use - 15 - LH28F320S3TD-L10 voltage. RP# must OUTPUT OFFSET ADDRESS ...
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... Maximum Time-Out per Maximum Size Buffer Write 04H (2 = 16, 64 µ 024 µs) Maximum Time-Out per Individual Block Erase 04H (2 = 16, 1 024 384 ms) Maximum Time-Out for Bank Erase 04H (2 = 16, 32 768 524 288 ms LH28F320S3TD-L10 N times of typical. N times of typical. N times of typical. N times of typical. ...
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... Bytes ) Number of Erase Block Regions within Device 01H (symmetrically blocked) The Number of Erase Blocks 1FH, 00H (1FH = Blocks) The Number of "256 Bytes" Cluster in a Erase Block 00H, 01H (0100H = 256 256 Bytes x 256 = 64 k Bytes in a Erase Block LH28F320S3TD-L10 ...
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... Block Status Register Lock Bit [BSR.0] active bit1 = 1 : Block Status Register Valid Bit [BSR.1] active bit2- Reserved for future use V Logic Supply Optimum Write/Erase voltage (highest performance) CC 50H (5 Programming Supply Optimum Write/Erase voltage (highest performance) PP 50H (5.0 V) Reserved for future versions of the SCS specification - 18 - LH28F320S3TD-L10 ...
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... SR.3 and SR.5 will be set to "1". When PPLK WP all blocks are erased independent of IH block lock-bits status. When WP unlocked blocks are erased. In this case, SR.1 and SR.4 will not be set to "1". Bank erase can not be suspended LH28F320S3TD-L10 = the absence of this PPH1/2/3 ≤ only IL ...
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... XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F320S3TD-L10 has two buffers error occurs while writing, the device will stop writing and flush next Multi Word/Byte Write ...
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... Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR LH28F320S3TD-L10 . After the Erase Resume OL (the same V level PPH1/2/3 PP ...
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... SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when CC1/2 lock-bits operation is attempted while V SR.3 and SR.5 will be set to "1". In the absence this high voltage, the block lock-bit contents are PP PPH1/2 LH28F320S3TD-L10 , SR.1 IL and clear block PP PPH1/2/3 ≤ PPLK ...
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... V Set Block Lock-Bit Enabled IH V Clear Block Lock-Bits Disabled IL V Clear Block Lock-Bits Enabled LH28F320S3TD-L10 voltage and EFFECTS Set STS pin to default level mode (RY/BY#). RY/BY# in the default level-mode of operation will indicate WSM status condition. Set STS pin to pulsed output signal for specific erase operation ...
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... NOTES : After issue a Multi Word/Byte Write command : XSR.7 indicates that a next Multi Word/Byte Write command is available. XSR.6-0 are reserved for future use and should be masked out when polling the extended status register LH28F320S3TD-L10 WSS DPS level. PP level only after PP ≠ V ...
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... Check SR.5 Standby 1 = Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 ...
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... Check SR.5 Standby 1 = Bank Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 ...
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... Standby 1 = Data Write Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 COMMENTS COMMENTS ...
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... SR full status check can be done after each multi word/byte write or after a sequence of multi word/byte writes. Write FFH after the last multi word/byte write operation to place device in read array mode. Write Loop - 28 - LH28F320S3TD-L10 COMMENTS Data = E8H Addr = Start Address Extended Status Register Data Check XSR.7 ...
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... Check SR.4 Standby 1 = Data Write Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 ...
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... Erase Write Suspend Read Standby Standby Erase Write Resume Block Erase Completed Write FFH Read Array Data - 30 - LH28F320S3TD-L10 COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Block Erase Suspended 0 = Block Erase Completed Data = D0H Addr = X ...
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... Addr = X Check SR WSM Ready Standby 0 = WSM Busy Check SR (Multi) Word/Byte Write Standby Suspended 0 = (Multi) Word/Byte Write Completed Data = FFH Write Read Array Addr = X Read array locations other Read than that being written. (Multi) Word/Byte Data = D0H Write Write Resume Addr = LH28F320S3TD-L10 ...
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... Set Block Lock-Bit Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple block lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 ...
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... Device Protect Detect WP Check SR.4, 5 Standby Both 1 = Command Sequence Error Check SR.5 Standby 1 = Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery LH28F320S3TD-L10 ...
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... If V error is detected, status register bit SR set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V during block erase, bank erase, (multi) word/byte write or block lock-bit configuration, STS (if set LH28F320S3TD-L10 decoupling. System PP CC power supply PP CC supply traces and ...
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... RP# is first raised to V 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and Fig. 15, Fig. 16, Fig. 17 and Fig. 18 for more information. PP when V is LKO PP will inhibit LH28F320S3TD-L10 standby or sleep modes and t wake-up cycles PHQV PHWL . See Section IH ...
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... Output shorted for no more than one second. No more than one output shorted at a time. MIN. MAX. 0 +70 2.7 3.6 3 MHz ˚ A NOTE TYP. MAX LH28F320S3TD-L10 Maximum Ratings" may cause pins. During transitions, this level may +0 +2 UNIT TEST CONDITION Ambient Temperature ˚ UNIT TEST CONDITION 0.0 V ...
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... R DEVICE UNDER TEST C C Includes Jig L Capacitance Fig. 14 Transient Equivalent Testing Load Circuit 1.35 TEST POINTS 1.5 TEST POINTS Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, 2 OUT LH28F320S3TD-L10 1.35 OUTPUT = 2 1.5 OUTPUT = 3.3±0 (pF ...
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... LH28F320S3TD-L10 TEST UNIT CONDITIONS MAX Max ±0.5 µ GND Max ±0.5 µ GND OUT CC CMOS Inputs 100 µ Max BE ±0 TTL Inputs Max BE RP# = GND±0 µA I (STS ...
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... If the bank0 is in write state and bank1 read state, the I PPLK (max.) and in standby mode, the value for the device is 2 times the PPH1 (min.) value in the above table. PPH3 - 39 - LH28F320S3TD-L10 TEST UNIT CONDITIONS MAX Min ...
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... OE# may be delayed ELQV GLQV 3. Sampled, not 100% tested. C ˚ NOTE NOTE after the falling edge of BE# without impact LH28F320S3TD-L10 (NOTE 1) LH28F320S3TD-L10 TYP. MAX. 120 120 120 600 120 30 5 LH28F320S3TD-L10 TYP. MAX. 100 100 100 600 100 ELQV UNIT UNIT ...
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... High Z DATA (D/ RP# ( NOTE : defined as the latter and Fig Waveform for Read Operations Device Address Selection Data Valid Address Stable t AVAV t GLQV t ELQV t GLQX t ELQX Valid Output t AVQV t PHQV #, BE # going Low or the first LH28F320S3TD-L10 t EHQZ t GHQZ t OH High Z # and going High ...
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... Address Selection Data Valid Address Stable t AVAV AVFL ELFL t ELFL FLQV AVQV t GLQV t ELQV t GLQX t ELQX Data Output t AVQV t FLQZ Data Output #, BE # going Low or the first Fig. 16 BYTE# Timing Waveforms - 42 - LH28F320S3TD-L10 t EHQZ t GHQZ t OH High Z Valid Output High Z # and going High ...
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... V PP block erase, bank erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4 LH28F320S3TD-L10 LH28F320S3TD-L10 UNIT MIN. MAX. 120 ns 1 µ 100 ns 100 100 LH28F320S3TD-L10 UNIT MIN. MAX. 100 ns 1 µ 100 ns 100 100 and D for block erase until determination of PPH1/2/3 ...
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... BE X High. Fig Waveform for WE#-Controlled Write Operations (NOTE 3) (NOTE AVAV AVWH WHAX t WHEH t WHGL t t WHWL WHQV1/2/3/4 t WLWH t DVWH t WHDX WHRL t SHWH t VPWH # and going Low or the first LH28F320S3TD-L10 (NOTE 5) (NOTE 6) Valid D IN SRD t QVSL t QVVL # and going ...
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... NOTE MIN. 100 100 2 100 Refer to Table 3 for valid A bank erase, (multi) word/byte write or block lock-bit configuration should be held PPH1/2/3 block erase, bank erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4 LH28F320S3TD-L10 UNIT MAX. ns µ 100 UNIT MAX. ns µ 100 ...
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... BE X High. Fig Waveform for BE#-Controlled Write Operations (NOTE 3) (NOTE AVAV AVEH EHAX t EHWH t EHGL t t EHEL EHQV1/2/3/4 t ELEH t DVEH t EHDX EHRL t SHEH t VPEH # and going Low or the first LH28F320S3TD-L10 (NOTE 5) (NOTE 6) Valid D IN SRD t QVSL t QVVL # and going ...
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... Reset AC Specifications V CC NOTE MIN 100 100 3. When the device power-up, holding RP#-low minimum 100 ns is required after V range and also has been in stable there LH28F320S3TD-L10 = 2 3.3±0 MAX. MIN. MAX. 100 21.5 21.1 100 has been in predefined CC UNIT ns µ ...
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... Excludes system-level overhead. 3. Sampled, not 100% tested LH28F320S3TD-L10 V = 5.0±0 (NOTE 1) (NOTE 1) MAX. MIN. TYP. MAX. 22.17 13.2 19.89 13.2 5.76 2.76 0.91 0.44 1.63 0.87 0.37 0.18 0.56 ...
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... MIN. TYP. 2 21.75 2 19.51 2 5.66 2 0.89 2 1.6 2 0.36 2 0.55 17.6 2 21.75 2 0.55 7.1 10 15.2 21.1 2. Excludes system-level overhead. 3. Sampled, not 100% tested LH28F320S3TD-L10 V = 5.0±0 UNIT (NOTE 1) MAX. 12.95 µs 12.95 µs 2.7 µs 0.43 s 0.85 s 0.18 s 0.41 s 13.1 s 12.95 µs 0. ...
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... Operating Temparature = 0 to +70 C OPTION ORDER CODE 1 LH28F320S3TD-L10 - Access Speed (ns 100 ns (3.3 0.3 V), 120 ns (2.7 to 3.6 V) Dual Work technology Package T = 56-pin TSOP (I) (TSOP056-P-1420) Normal bend VALID OPERATIONAL COMBINATIONS V = 2 load, 1.35 V I/O Levels 120 LH28F320S3TD-L10 V = 3.3±0 load, 1.5 V I/O Levels 100 ns ...
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TSOP (TSOP056-P-1420 0.3 20.0 18.4 0.2 0.3 19.0 PACKAGING Package base plane ...