LH28F640BFHG-PBTLE7 Sharp, LH28F640BFHG-PBTLE7 Datasheet
LH28F640BFHG-PBTLE7
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LH28F640BFHG-PBTLE7 Summary of contents
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... P S RODUCT PECIFICATION LH28F640BFHG-PBTLE7 Flash Memory 64Mbit (4Mbitx16) (Model Number: LHF64FE7) Spec. Issue Date: December 1, 2004 Spec No: EL16Z002 Integrated Circuits Group ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, ...
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CSP (8mm×11mm) Pinout ..... 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address for ...
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... LH28F640BFHG-PBTLE7 Page Mode Dual Work Flash MEMORY 64M density with 16Bit I/O Interface High Performance Reads • 80/35ns 8-Word Page Mode Configurative 4-Plane Dual Work • Flexible Partitioning • Read operations during Block Erase or (Page Buffer) Program • Status Register for Each Partition Low Power Operation • ...
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LHF64FE7 WP WE# A RST ...
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Symbol Type A -A ADDRESS INPUTS: Inputs for addresses. 64M: A INPUT 0 21 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, INPUT/ DQ -DQ identifier ...
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Table 2. Simultaneous Operation Modes Allowed with Four Planes THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE Read Read Read PARTITION IS: Array ID/OTP Status Read Array Read ID/OTP Read Status ...
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LHF64FE7 BLOCK NUMBER ADDRESS RANGE 134 32K-WORD 3F8000H - 3FFFFFH 133 3F0000H - 3F7FFFH 32K-WORD 132 3E8000H - 3EFFFFH 32K-WORD 131 3E0000H - 3E7FFFH 32K-WORD 130 3D8000H - 3DFFFFH 32K-WORD 129 3D0000H - 3D7FFFH 32K-WORD 128 32K-WORD 3C8000H - 3CFFFFH ...
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Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Bottom Parameter Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code ...
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LHF64FE7 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ - Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP ...
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Table 5. Bus Operation Mode Notes RST# CE# Read Array Output Disable Standby Reset Read Identifier Codes/OTP V V Read Query 6,7 ...
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Command Cycles Req’d Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set ...
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... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP WP lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. IH 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF64FE7 11 ...
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Table 7. Functions of Block Lock Current State (1) State WP [000 (3) [001] [011 [100 (3) [101 ...
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Table 9. Block Locking State Transitions upon WP# Transition Current State Previous State State WP# - [000 [001] 0 (2) [110] [011] 0 Other than (2) [110] - [100 [101 [110 [111] ...
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WSMS BESS BEFCES SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS ...
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Table 11. Extended Status Register Definition SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page ...
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Table 12. Partition Configuration Register Definition PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 ...
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Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except V and V ).............. ...
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Capacitance (1) (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance C IN Output Capacitance C OUT NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT 0.0 AC test inputs are driven at V Input ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read CC ...
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Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Normal PP V PPLK Operations V during Block Erase, Full Chip PP V Erase, (Page ...
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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...
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(A) (A) 21-0 20 EHEL V IH CE# ( AVEL t AVGL t GHGL V IH OE# ( (W) WE High Z OH ...
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(A) (A) 21-3 20 (A) 2 CE# ( OE# ( WE# ( High ...
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(A) (A) 21-3 20 AVQV V IH VALID A (A) 2-0 ADDRESS CE# ( ELQV V IH OE# ( WE# (W) V ...
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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...
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NOTE 1 NOTE VALID A A (A) (A) 21-0 20-0 ADDRESS AVAV V IH CE# ( ELWL WLEL V IH OE# ( PHWL PHEL ...
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Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...
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Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
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... Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF64FE7 (1) Document Name LH28F640BF series Appendix 29 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv ...
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A-3 STATUS REGISTER READ OPERATIONS If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program operation ...
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... Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. ...