LH28F128BFHED-PWTL90 Sharp, LH28F128BFHED-PWTL90 Datasheet
LH28F128BFHED-PWTL90
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LH28F128BFHED-PWTL90 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F128BFHED-PWTL90 Flash Memory Issue Date: February 26, 2002 ® 128M (8M × 16) (Model No.: LHF12F01) Spec No.: EL142079 Integrated Circuits Group ...
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... Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs ...
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... TSOP Pinout................................................. 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 8 Identifier Codes and OTP Address for Read Operation on Partition Configuration........ 8 OTP Block Address Map for OTP Program............... 9 Bus Operation........................................................... 10 Command Definitions ...
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... LH28F128BFHED-PWTL90 Page Mode Dual Work Flash MEMORY 128M density with 16Bit I/O Interface • 2 Bank Enable ( Control 0 1 High Performance Reads • 90/35ns 8-Word Page Mode Configurative 8-Plane Dual Work • Flexible Partitioning • Read operations during Block Erase or (Page Buffer) Program • ...
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... WE# 11 RST WP LHF12F01 48-LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW Figure 1. 48-Lead TSOP (Normal Bend) Pinout GND OE# 28 GND Rev. 2.41 ...
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... Symbol Type A -A ADDRESS INPUTS: Inputs for addresses. A INPUT 0 21 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, INPUT/ DQ -DQ identifier code and partition configuration register code reads. Data pins float to high- ...
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... Table 2. Simultaneous Operation Modes Allowed with Eight Planes THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page Buffer X X Program ...
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... BLOCK NUMBER ADDRESS RANGE 134 4K-WORD 133 4K-WORD 132 4K-WORD 131 4K-WORD 130 4K-WORD 129 4K-WORD 128 4K-WORD 127 4K-WORD 126 32K-WORD 125 32K-WORD 124 32K-WORD 123 32K-WORD 122 32K-WORD 121 32K-WORD 120 32K-WORD 119 32K-WORD 118 32K-WORD 117 32K-WORD ...
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... Selected by BE #=V 1 BLOCK NUMBER ADDRESS RANGE 134 32K-WORD 133 32K-WORD 132 32K-WORD 131 32K-WORD 130 32K-WORD 129 32K-WORD 128 32K-WORD 127 32K-WORD 126 32K-WORD 125 32K-WORD 124 32K-WORD 123 32K-WORD 122 32K-WORD 121 32K-WORD 120 32K-WORD 119 32K-WORD 118 ...
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... Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code Partition Configuration Register OTP OTP Lock OTP NOTES: 1 ...
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... Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block Address Map for OTP Program NOTE: 1. When the OTP program operation is executed, write the OTP Program command with BE OTP block in Bank 1 (selected by BE ...
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... Mode Notes Bank 0 Bank 1 Read Array 6 Inhibited Output Disable Bank 0 Bank 1 Standby Bank 0, 1 Reset 3 Bank 0 Read Identifier 6,9 Bank 1 Codes/OTP Inhibited Bank 0 Bank 1 Read Query 6,7 Inhibited Bank 0 4,5, Bank 1 Write 6,8 Inhibited NOTES: 1. Refer to DC Characteristics. When can be V ...
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... Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Bank Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit ...
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... IH 11. When the data within OTP block is read, BE Program command with 12. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF12F01 # must When the OTP program operation is executed, write the OTP 0 IL ...
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... Table 7. Functions of Block Lock State WP# [000] 0 (3) 0 [001] [011] 0 [100] 1 (3) 1 [101] (4) 1 [110] [111] 1 NOTES =1: a block is locked =1: a block is locked-down Erase and program are general terms, respectively, to express: block erase, bank erase and (page buffer) program operations power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation ...
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... Table 9. Block Locking State Transitions upon WP# Transition Previous State State - [000] - [001] (2) [110] [011] (2) Other than [110] - [100] - [101] - [110] - [111] NOTES: 1. "WP#=0→1" means that WP# is driven State transition from the current state [011] to the next state depends on the previous state. ...
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... WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND BANK ERASE STATUS (BEFCES Error in Block Erase or Bank Erase 0 = Successful Block Erase or Bank Erase SR ...
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... SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) LHF12F01 Table 11. Extended Status Register Definition After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. ...
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... Table 12. Partition Configuration Register Definition PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in Bank 1 selected by BE 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively ...
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... Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except V and V ).............. -0. Supply Voltage ........................... -0.2V to +3.9V ...
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... Capacitance (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance C Output Capacitance C OUT NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CC INPUT 0.0 AC test inputs are driven at V Input timing begins, and output timing ends at V Worst case speed conditions are when V Figure 5 ...
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... DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read CC Current Normal Mode I CCR Average V Read CC 8 Word Read Current Page Mode I V (Page Buffer) Program Current ...
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... Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Normal PP V PPLK Operations V during Block Erase, Bank Erase (Page Buffer) Program or OTP Program PPH1 Operations V during Block Erase, (Page Buffer) ...
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... AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV Output Delay ELQV Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to Output Delay PHQV OE# to Output in High Z, Whichever Occurs EHQZ GHQZ First Output in Low Z ...
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... (A) (A) 21-0 20 CE OE# ( (W) WE High (D/Q) 15 (P) RST Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code LHF12F01 VALID ADDRESS t AVQV t ELQV t GLQV t GLQX t ELQX t PHQV 23 t EHQZ t GHQZ t OH VALID OUTPUT ...
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... (A) (A) 21-3 20 (A) 2 ( OE# ( (W) WE High (D/Q) 15 (P) RST Figure 8. AC Waveform for Asynchronous Page Mode Read Operations LHF12F01 VALID ADDRESS t AVQV VALID VALID ADDRESS ADDRESS t ELQV t GLQV t GLQX t APA t ELQX VALID VALID OUTPUT OUTPUT t PHQV from Main Blocks or Parameter Blocks ...
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... AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (BE PHWL PHEL (WE#) Setup to WE# ( ELWL WLEL Going Low WE# ( WLWH ELEH Data Setup to WE# (BE DVWH DVEH Address Setup to WE# (BE AVWH AVEH (WE#) Hold from WE# ( WHEH EHWH High Data Hold from WE# (BE ...
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... NOTE 1 NOTE VALID A A (A) (A) 21-0 20-0 ADDRESS ( ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# ( (D/Q) 15 "1" SR.7 (R) "0" RST# ( WP# ( PPH1 PPLK V IL NOTES power-up and standby Write each first cycle command. 3. Write each second cycle command or valid address and data. ...
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... Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V IH RST# ( High (D/Q) 15 Reset AC Specifications (V Symbol RST# Low to Reset during Read t PLPH (RST# should be low during power-up.) t RST# Low to Reset during Erase or Program PLRH t V 2.7V to RST# High ...
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... Block Erase, Bank Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 OTP Program Time t EHOV1 t / 4K-Word Parameter Block WHQV2 ...
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... Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF12F01 (1) Document Name LH28F128BF series Appendix 29 Rev. 2.41 ...
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... A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. V (min GND V IH RP# (P) (RST CCWH1 PPH1/2 ...
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... A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Parameter Notes Min. ...
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... A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) Acceptable Glitch Noises See the “DC CHARACTERISTICS“ described in specifications for V (Min ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. ...