MT8941AE Zarlink Semiconductor, MT8941AE Datasheet
MT8941AE
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MT8941AE Summary of contents
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Features • Provides T1 clock at 1.544 MHz locked kHz reference clock (frame pulse) • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock ...
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... When DPLL # SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal provided by DPLL #1 which is also connected internally to DPLL # VDD 23 RST CVb MS1 Yo 20 F0i 19 Bi F0b 18 Ai MS2 17 MS3 C16i 16 ENC2o ENC4o 15 C2o 14 C2o 13 C4b Figure 2 - Pin Connections Description Zarlink Semiconductor Inc. Data Sheet • CVb MS3 11 19 ENC2o 28 PIN PLCC ...
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... Figures 9-13) must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60nsec to reset the device (+5V) Power supply Connection. 5, 18, 25 Description (pin 16). C2o (pin 16). C2o Zarlink Semiconductor Inc. MT8941B (pin 1 ...
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... P16 P16 = 766 × CSF P16 is the 12.352 MHz master clock oscillator period P12 is the 16.384 MHz master clock period P16 Figure 4 - Phase Comparison Zarlink Semiconductor Inc. ÷ 8 Output (1.544 MHz / 2.048 MHz) ÷ 193 / ÷ 256 slow-down region Data Sheet ...
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... These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE-RUN mode if the C8Kb pin is tied Zarlink Semiconductor Inc. MT8941B 5 ...
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... Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal CLOCK-1 provided by DPLL #1. SINGLE Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal CLOCK-2 provided by DPLL #1. Table 2 - Major Modes of DPLL #2 Zarlink Semiconductor Inc. Data Sheet Function Function ...
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... C8Kb. Minor modes of DPLL #2 The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17). Functional Description Table 3 - Minor Modes of DPLL #2 Zarlink Semiconductor Inc. MT8941B 7 ...
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... Same as mode ‘0’. SINGLE CLOCK-2 MODE: F0b is an input but has no function in this mode. Same as mode 2. SINGLE CLOCK-2 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1. Zarlink Semiconductor Inc. Data Sheet DPLL #2 ...
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... Output X: “don’t care” input. Connect to V Zarlink Semiconductor Inc. CVb (MHz) i:X o:1.544 i:8 o:1.544 i:X o:1.544 i:8 o:1.544 i:X i:1.544 o:8 i:1.544 i:X i:1.544 o:8 i:1.544 i:X o:1 ...
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... Table 6 - Lock-in Range vs. Oscillator Frequency Tolerance Figure 5 - The Spectrum of the Inherent Jitter for either PLL 10 Lock-in Range (±Hz) DPLL #1 5 2.55 10 2.51 20 2.43 32 2.33 50 2.19 100 1.79 150 1.39 175 1.19 Zarlink Semiconductor Inc. Data Sheet DPLL #2 1.91 1.87 1.79 1.69 1.55 1.15 .75 .55 ...
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... DPLL #1 has no impact on its output clock tolerance. For this reason recommended to use a ±32 ppm oscillator for DPLL #2 and a ±100 ppm oscillator for DPLL #1. Figure 6 - The Jitter Transfer Function for PLL1 Figure 7 - The Jitter Transfer Function for PLL2 Zarlink Semiconductor Inc. MT8941B 11 ...
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... Reference Signal b) Centralized Timing 8 kHz Reference Signal M U MT8941B X Clocks 8 kHz Reference Signal Figure 8 - Application Differences between the MT8940 and MT8941B 12 Data Bus MT8940 MT8940 Data Bus Zarlink Semiconductor Inc. Data Sheet Line Card 1 Clocks Line Card n Clocks Line Card 1 Line Card n ...
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... MH89760/760B. The crystal clock at 12.352 MHz is used by DPLL #1 to generate the 1.544 MHz clock, while DPLL #2 (in FREE-RUN mode) uses the 16.384 MHz crystal oscillator to generate the ST-BUS clocks for system timing. The generated ST-BUS signals can be used to synchronize the system and the switching equipment at the master end. Zarlink Semiconductor Inc. MT8941B 13 ...
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... EN CV C8Kb C2o C16i EN C4o F0b EN C2o V RST SS DPLL #1 - NORMAL ( MS1= DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) DD Zarlink Semiconductor Inc. MT8980/81 ST-BUS MH89760B SWITCH C1.5i DSTi C2i DSTo F0i CSTi CSTo TxT TRANSMIT TxR RxT (1.544 Mbps) RECEIVE RxR Mode of Operation for the MT8941B ...
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... V DD C4b C2i F0i C2o CV F0b C4o C2o Y o RST V DD DPLL #1 - NOT USED R C DPLL #2 - FREE-RUN Zarlink Semiconductor Inc. MT8980/81 MH89790B ST-BUS SWITCH DSTi DSTo CSTi0 CSTi1 CSTo OUTA TRANSMIT PRIMARY OUTB MULTIPLEX DIGITAL RxT RECEIVE RxR Mode of Operation for the MT8941B (MS0=1 ...
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... DD C4b C2i F0i C2o CV E8Ko F0b C4o C2o RST V DPLL #1 - NOT USED DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) Zarlink Semiconductor Inc. MT8980/81 ST-BUS MH89790B SWITCH DSTi DSTo CSTi0 CSTi1 CSTo OUTA CEPT TRANSMIT PRIMARY OUTB MULTIPLEX DIGITAL RxT LINK RECEIVE RxR ...
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... MS2=1; MS3= Voltages are with respect to ground (V - PLCC - Voltages are with respect to ground (V ‡ Sym Min Typ V 4 Zarlink Semiconductor Inc. MT8941B V MS0 DD MS1 MS2 C4o MS3 F0i C4b C12i EN CV C8Kb C2o C16i EN C4o C2o EN C2o Ai F0b Bi V RST ...
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... Min Typ 2 3 1.0 1 -100 - ±1 I -10 IL Zarlink Semiconductor Inc. Data Sheet ) unless otherwise stated. SS Max Units Test Conditions 15 mA Under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up /down resistors. V 4 µ µA ...
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... Voltages are with respect to ground (V ‡ Sym Min Typ Max C8HH t 13 C8LL ICHL ICLH Zarlink Semiconductor Inc. MT8941B (Refer to Figure 14) ) unless otherwise stated. SS Units Test Conditions Load Load 689 ns 324 ns 363 (Refer to Figure 15) ) unless otherwise stated. SS Units Test Conditions ...
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... OL t W4oL V OH C4o 42LH t 42HL V OH C2o W2oL V OH C2o V OL Figure 16 - Timing Information on DPLL #2 Outputs 20 Figure 15 - DPLL #1 in DIVIDE Mode t WFP t FPH t fC4 t t 4oLH 4oHL t P2o t W2oH t 2oLH Zarlink Semiconductor Inc. Data Sheet t P4o t rC4 t rC2 t fC2 t 2oHL ...
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... P2o t 207 W2oH t 238 W2oL t 6 rC2 t 6 fC2 t -5 2oLH 2oHL Zarlink Semiconductor Inc. MT8941B (Refer to Figure 16) ) unless otherwise stated. SS Units Test Conditions 275 Load 159 ns 122 Load Load 85 pF Load Load 8 ns 245 ns 15 ...
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... Voltages are with respect to ground (V ‡ Sym Min Typ t 244 WFP t 244 P4o Zarlink Semiconductor Inc. Data Sheet (Refer to Figure 14) ) unless otherwise stated. SS Max Units Test Conditions For DPLL #1, while operating to 80.974 ns provide the T1 clock signal. For DPLL #2, while operating to 61.046 ...
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... Voltages are with respect to ground (V ‡ Sym Min Typ t PHZ t PLZ t PZH t 50 PZL PZL 10% t PZH 90% Outputs Disabled Zarlink Semiconductor Inc. MT8941B (Refer to Figure 19) ) unless otherwise stated. SS Max Units Test Conditions Load Load Load Load 3.0 V 2.7 V 1.3 V 0 ...
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... Typical figures are and are for design aid only: not guaranteed and not subject to production testing. 24 † - Uncommitted NAND Gate ) unless otherwise stated. ‡ Sym Min Typ t PLH t PHL Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions Load Load ...
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