5962-9759701QXA Cypress Semiconductor Corporation., 5962-9759701QXA Datasheet
5962-9759701QXA
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5962-9759701QXA Summary of contents
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Features • 128 macrocells in eight logic blocks • 128 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable (ISR™) Flash technology — JTAG Interface • Bus Hold capabilities on all I/Os and dedicated inputs • ...
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Pin Configurations GND I/O /SCLK GND ...
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Pin Configurations (continued) GND I/O /SCLK GND I/O 26 ...
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Pin Configurations (continued) R I/O I/O I/O 109 112 115 P I/O I/O I/O 106 110 113 I/O 108 N I/O I/O 105 111 /SDI M I/O I/O I/O 102 104 107 L I/O I/O I/O 100 101 103 K ...
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Product term steering and product term sharing help to increase the effective density of the F 370i PLDs. Note that product term allocation is han- LASH dled by software and is invisible to the ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output HIGH Voltage OHZ with Output Disabled V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Load Current ...
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Inductance Parameter Description L Maximum Pin Inductance [9] Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles AC Test Loads and Waveforms 238 (COM’L) 319 (MIL) 5V OUTPUT 35 pF 170 (COM’L) 236 (MIL) INCLUDING JIG AND (a) SCOPE Equivalent ...
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Switching Characteristics Over the Operating Range Parameter Description Combinatorial Mode Parameters t Input to Combinatorial Output PD t Input to Output Through Transparent Input PDL [1] or Output Latch t Input to Output Through Transparent Input PDLL [1] and Output ...
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Switching Characteristics Over the Operating Range Parameter Description Pipelined Mode Parameters t Input Register Clock to Output Register ICS Clock f Maximum Frequency in Pipelined Mode MAX4 (Least of 1/( 1 1/( ...
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Switching Waveforms (continued) Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03029 Rev ...
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Switching Waveforms (continued) Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03029 Rev PDL ...
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Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03029 Rev ...
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... Standard product ships trim and formed in a carrier. This product is also available in a molded carrier ring. Contact local Cypress office for package information. ISR, UltraLogic, F 370 and F LASH LASH Warp, Warp Professional, and Warp Enterprise are registered trademarks of Cypress Semiconductor Corporation. Document #: 38-03029 Rev. ** Package Name Package Type ...
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Package Diagrams Document #: 38-03029 Rev. ** 160-Pin Thin Plastic Quad Flat Pack (TQFP) A160 CY7C375i 51-85049-A Page ...
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Package Diagrams (continued) Document #: 38-03029 Rev. ** 160-Pin PGA G160 CY7C375i Page ...
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Package Diagrams (continued) Document #: 38-03029 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in ...
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Document Title: CY7C375i UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03029 Issue REV. ECN NO. Date ** 106374 09/15/01 Document #: 38-03029 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00494 to 38-03029 CY7C375i Page 17 ...