LE78D110VC Zarlink Semiconductor, LE78D110VC Datasheet
LE78D110VC
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LE78D110VC Summary of contents
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... Legerity Holdings. Le78D11 Integrated Voice Chip Sets ORDERING INFORMATION A Legerity VoSLIC™ device must be used with this part. Device LE78D110VC 44-pin TQFP LE78D110BVC 44-pin TQFP (Green package)* *Green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. ...
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... PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Single Channel Application Circuit with the Le77D11 Device .29 Application Circuit Parts List for the Le77D11 Device .30 Physical Dimensions .31 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Revision .32 Revision .32 Revision .32 2 Zarlink Semiconductor Inc. ...
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... Figure 14. PCM Highway Timing for (Transmit on Positive PCLK Edge .25 Figure 15. Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 16. Chopper Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 17. Input and Output Waveforms for AC tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 18. 4.096 MHz DCL GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 19. 2.048 MHz DCL GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3 Zarlink Semiconductor Inc. ...
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... Adaptive Transhybrid Balance filter is included that allows the Le78D11 VoSLAC device to dynamically adjust to changing line conditions minimizing objectionable echo. All programmable digital filter coefficients can be calculated using WinSLAC software. The PCM codes can be either 16-bit linear two's complement, 8-bit companded A-law or µ-law kbit kbit/s ADPCM. 4 Zarlink Semiconductor Inc. ...
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... Generator Processing PCM Interface 2 and Time Slot 2 Assigner (TSA Microprocessor 1 Interface 1 SLIC Interface (MPI) (SLI Band Gap 2 Voltage Reference 5 Zarlink Semiconductor Inc. Line Measurement MCLK PCLK/FSC FS/DCL DRA/DD DXA/DU TSCA/G DCLK DIN/S1 INT/S2 DOUT RST VREF IREF ...
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... Device Configuration Register 1 accordingly to provide the required reference. In the PCM/MPI mode, the reference input clock can be derived from either PCLK or MCLK. The clock being supplied must be communicated to the Le78D11 VoSLAC device using the MPI by specifying its source and frequency in Device Configuration 6 Zarlink Semiconductor Inc. ...
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... VS Le78D11 VoSLAC device inputs and VREF to form voltage dividers Zarlink Semiconductor Inc and C1 control pins. The Description Voice transmission disabled. Maximum loop current capability and loop current sensing range are reduced. ...
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... When ADPCM at 32 kbps or 24 kbps (as defined in ITU recommendation G.726. pin above the IMT TEMPA threshold voltage. The Le78D11 VoSLAC device sets which is rectified and averaged over period. Whenever the sum bits in the Global Device Status register. The i 8 Zarlink Semiconductor Inc. ...
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... The Le78D11 VoSLAC device has the ability to generate phase continuous FSK tones at a 1200 baud rate. These tones can be used for a variety of purposes such as Calling Number Delivery (CND), better known as Caller ID, and Visual Message Waiting ) in order to modify the effective two-wire input impedance of the Le77D11 OUT 9 Zarlink Semiconductor Inc. ...
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... DGND 2 INT/S 2 Note: 1. Pin 1 is marked for orientation 44-pin TQFP Zarlink Semiconductor Inc. 33 IMT 1 32 VIN 1 31 AGND 1 30 VOUT 1 29 VCCA ...
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... Signaling and Global Interrupt Registers with their associated Mask Registers, and the Interrupt Register. See the description at configuration register 6 (Mask) for operation. Logic drive is selectable between open drain and TTL-compatible outputs. In GCI mode, this pin functions as device address bit 2. Active low reset for the Le78D11 VoSLAC device. 11 Zarlink Semiconductor Inc. ...
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... REF accurate, on-chip reference current for the A/D's and D/A's on the Le78D11 chip. This pin provides a 1.4 V, single ended reference to the Le77D11 device to which the Le78D11 VoSLAC device is connected. 12 Zarlink Semiconductor Inc. resistors. DCi = I • K IMT ...
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... V ± ± 50mV CCD +3.3 V ± ±10 mV DGND to +5.25V Test Conditions Two channels Standby One channel Active, one channel Standby Two channels Active 13 Zarlink Semiconductor Inc. ≤ + 85ºC + 2.37 V, whichever is CCD +0.4 V ≤ 85ºC A Min Typ Max 100 120 ...
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... 400 µA OH Drive low Drive high 0 < V < V CCD Otherwise 6. Load current = Source or Sink -6. Zarlink Semiconductor Inc. Min Typ Max Unit Note Ω 200 –20 +20 ...
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... TX RX Digital input = 0 A-Law Digital input = 0 µ-law VAC A-Law INi VAC µ-law INi A-D, Input signal = 0V Input: 4.8 to 7.8 kHz, 200 mV p-p Measure 8000 Hz-Input frequency A-D D-A 15 Zarlink Semiconductor Inc. Min Typ Max Unit –40 +40 mV –80 +80 –10 10 µA Ω 3490 1 MΩ ...
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... Hz to 3400 Hz 0 dBm0 300 Hz to 3400 12.0 kHz or 16.0 kHz 12.0 kHz or 16.0 kHz, 0.5 Vpk 0.5 Vpk (MVO = 3F) from kHz 12.0 kHz or 16.0 kHz –1.5 – 15% –2.5– 20% 16 Zarlink Semiconductor Inc. Min Typ Max Unit –75 dBm0 –75 –76 dBm0 –78 µS 525 ± ...
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... Figure 2 and Figure 2. Transmit Path Attenuation vs. Frequency 2 1 0.6 0.125 0 -0.125 0 Figure 3. Receive Path Attenuation vs. Frequency 2 1 0.6 0.125 0 -0.125 0 Figure 3. The reference frequency is 1014 Hz and the signal level is Acceptable Region Frequency (Hz) Acceptable Region Frequency (Hz) 17 Zarlink Semiconductor Inc. – 10 dBm0. 0.80 0.65 0.2 0.80 0.65 0.2 ...
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... Figure 5. A-law Gain Linearity with Tone Input (Both Paths) 0.55 0.25 Gain (dB) -0.25 -0.55 -1.5 Figure 4. Group Delay Distortion Acceptable Region 0 Frequency (Hz) 1.5 Acceptable Region 0 -55 -50 -40 18 Zarlink Semiconductor Inc. Figure 4. The minimum value of the group Figure 5 (A-law) and Figure 6 (µ-law) for either Input Level - (dBm0) ...
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... Digital voice output connected to digital voice input. 4. Measurement analog to analog. Fundamental Output Power (dBm0) Acceptable Region 0 -55 -50 -37 Figure 7. A/A Overload Compression 2 Fundamental Input Power (dBm0) 19 Zarlink Semiconductor Inc. Input Level +3 -10 0 (dBm0) Acceptable Region ...
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... A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 π 4000 f – ( ---------------------------- - Attenuation (db – sin 1200 20 Zarlink Semiconductor Inc. A A-Law µ-Law A 35.5dB 35.5dB B 35.5dB 35.5dB C 30dB 31dB D 25dB 27dB ...
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... Hz and 4600 Hz is given by the formula: -28 dBm -32 dB, -25 dBm0 < input , 0 dBm0 Acceptable Region 3.4 4.0 4.6 Frequency (kHz) Figure π f 4000 ( ) – ---------------------------- - A = – 14 – 14 sin dBm0 1200 21 Zarlink Semiconductor Inc. Level –32 dBm0 –46 dBm0 –36 dBm0 10. The amplitude of the spurious out-of-band ...
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... ODOF t 20 Output data valid ODC t 21 Reset pulse width RST Figure 10. Spurious Out-of-Band Signals 0 -10 -20 -30 -40 Acceptable Region -50 3.4 4.0 4.6 Frequency (kHz) Parameter 22 Zarlink Semiconductor Inc. -28 dBm -32 dB Min Typ Max Unit 122 –10 30 DCY t –20 0 DCH 8t DCY 2000 ...
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... Figure 12. Microprocessor Interface (Output Mode DCLK High Impedance D OH Bit 7 OUT Data Valid Bit 0 Data Data Valid Valid Data Valid Data Bit 0 Valid Data Valid 23 Zarlink Semiconductor Inc Data Valid 16 19 High Impedance ...
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... Time Slot Zero, Clock Slot Zero First Bit First Second Bit Bit Zarlink Semiconductor Inc. Typ Max Unit 7.8125 µ –30 30 PCY ...
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... V OH First Bit First Second Bit Bit V IL Parameter Figure 15. Master Clock Timing Zarlink Semiconductor Inc. 30 4.. 33 Min Typ Max Unit 488.23 488.28 488.33 244.11 244.14 244.17 122.05 122.07 122. Note 6. ...
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... High pulse width Delay from DCL edge Delay from FS edge Data setup Data hold ⋅ , where f is the applied PCLK frequency. Once DCR1 is programmed for the f PCLK PCLK 26 Zarlink Semiconductor Inc. Typ Max Unit 11.71875 3.90625 t • CHCLKY µs 0.09375 t • ...
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... TTS is the transmit time slot and TCS is the transmit clock slot. PCY V OH 2.0 V TEST POINTS V OL 0.8 V VCC = 3.3 V +5%, AGND = DGND = 0 V Figure 18. 4.096 MHz DCL GCI Operation BIT 7 See Detail Below Zarlink Semiconductor Inc 0.8 V BIT Timing diagram valid for F = 4096 kHz DCL ...
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... Figure 19. 2.048 MHz DCL GCI Operation DCL FSC DD DCL FSC BIT 5 BIT 7 BIT 6 See Detail Below Zarlink Semiconductor Inc. 47 ...
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... W P10SCT-ND 180 Ω 1% 1/4 W Panasonic ERJ-6ENF1820V 1/16 W Panasonic / ERJ-3EKF2002V 69 1/16 W Panasonic / ERJ-3EKF6982V 100 K 1% 1/16 W Panasonic / ERJ-3EKF1003V 280 K 1% 1/16 W Panasonic / ERJ-3EKF2803V 475 K 1% 1/16 W Panasonic / ERJ-3EKF4753V 237 k 1% 1/8 W Panasonic / ERJ-8ENF2373V 1/16 W Panasonic / ERJ-3KF1002V Bourns / TISP61089BDR 30 Zarlink Semiconductor Inc. Comments Note PK ...
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... The top of package is smaller than the bottom of the package by 0.15mm. 12. This outline conforms to Jedec publication 95 registration MS-026 13. The 160 lead is a compliant depopulation of the 176 lead MS-026 variation BGA. 44-Pin TQFP 31 Zarlink Semiconductor Inc. ...
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... Revision • Enhanced format of package drawing in • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 = 0 to 70°C A Ordering Information, on page 1 ringing application in the VE 770 series PK Device DC Specifications, Physical Dimensions, on page 31 32 Zarlink Semiconductor Inc. Transmission Specifications, on page 15 on page 14 ...
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... I C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo are trademarks, and Legerity, the Legerity logo and combinations thereof are registered trademarks of Zarlink Semiconductor Inc. All other trademarks and registered trademarks are the property of their respective owners. © 2007 Zarlink Semiconductor Inc. All Rights Reserved. ...