MX29LV040QC-70 Macronix International Co., MX29LV040QC-70 Datasheet

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MX29LV040QC-70

Manufacturer Part Number
MX29LV040QC-70
Description
Manufacturer
Macronix International Co.
Datasheet

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FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8 only
• Single power supply operation
• Fast access time: 55R/70/90ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
GENERAL DESCRIPTION
The MX29LV040 is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29LV040 is
packaged in 32-pin PLCC and TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV040 offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29LV040 has separate chip enable (CE) and output
enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV040 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
P/N:PM0722
- 3.0V only operation for read, erase and program
operation
- 20mA maximum active current
- 0.2uA typical standby current
- 8 equal sector of 64K-Byte each
- Byte Programming (9us typical)
- Sector Erase (Sector structure 64K-Byte x8)
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
1
3V ONLY EQUAL SECTOR FLASH MEMORY
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
• Status Reply
• Sector protection
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
• Compatibility with JEDEC standard
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV040 uses a 2.7V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
then resumes the erase.
- Data polling & Toggle bit for detection of program and
erase operation completion.
- Hardware method to disable any combination of
sectors from program or erase operations
- Any combination of sectors can be erased with erase
suspend/resume function.
- Tempoary sector unprotect allows code changes in
previously locked sectors.
- 32-pin PLCC
- 32-pin TSOP
- Pinout and software compatible with single-power
supply Flash
ADVANCE INFORMATION
MX29LV040
REV. 0.7, JUL. 12, 2001

Related parts for MX29LV040QC-70

MX29LV040QC-70 Summary of contents

Page 1

FEATURES • Extended single - supply voltage range 2.7V to 3.6V • 524,288 x 8 only • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55R/70/90ns • Low power consumption ...

Page 2

PIN CONFIGURATIONS 32 TSOP (Standard Type) (8mm x 20mm) A11 A13 4 A14 5 A17 VCC 8 MX29LV040 A18 9 A16 10 A15 11 A12 ...

Page 3

BLOCK DIAGRAM CONTROL CE INPUT OE WE LOGIC ADDRESS LATCH A0-A18 AND BUFFER Q0-Q7 P/N:PM0722 MX29LV040 PROGRAM/ERASE HIGH VOLTAGE MX29LV040 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 WRITE STATE ...

Page 4

AUTOMATIC PROGRAMMING The MX29LV040 is byte programmable using the Auto- matic Programming algorithm. The Automatic Program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. The typical chip ...

Page 5

VID, as shown in table 3. To verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest or- der address bit (see Table 1 and ...

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TABLE 3. MX29LV040 COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Manufacturer ID 4 555H AAH 2AAH Read Silicon ID 4 555H AAH 2AAH Sector Protect 4 555H AAH 2AAH Verify ...

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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...

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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE and OE pins to VIL the power control and selects the device the output control and gates array ...

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SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM program- mers typically access ...

Page 10

READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. ...

Page 11

Table 6. Write Operation Status Status Byte Program in Auto Program Algorithm Auto Erase Algorithm In Progress Erase Suspended Mode Byte Program in Auto Program Algorithm Exceeded Time Limits Auto Erase Algorithm Erase Suspend Program Note and Q2 ...

Page 12

ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector ...

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WRITE OPERSTION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6 and Q7. Table 10 and the following subsections describe the functions of these bits. Q7 and Q6 each offer ...

Page 14

Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is ...

Page 15

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open high ("1") the internally ...

Page 16

CHIP UNPROTECT The MX29LV040 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotect mode. ...

Page 17

ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...

Page 18

Table 8. CAPACITANCE SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance READ OPERATION Table 9. DC CHARACTERISTICS Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ILO Output ...

Page 19

AC CHARACTERISTICS TA = -40 ( Table 11. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE to Output Delay tOE OE to Output Delay tDF OE High to Output ...

Page 20

Figure 1. SWITCHING TEST CIRCUITS DEVICE UNDER TEST Figure 2. SWITCHING TEST WAVEFORMS 3.0V 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are ...

Page 21

Figure 3. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE VIL VIH OE VIL HIGH Z VOH Outputs VOL VIH RESET VIL P/N:PM0722 MX29LV040 tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 21 tDF ...

Page 22

AC CHARACTERISTICS TA = -40 ( Table 11. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...

Page 23

AC CHARACTERISTICS TA = -40 ( Table 12. Alternate CE Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES ...

Page 24

Figure 4. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH Data VIL P/N:PM0722 ADD Valid tAH tWP tCWC tCH tDS tDH DIN 24 MX29LV040 tWPH REV. ...

Page 25

AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...

Page 26

Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM0722 MX29LV040 START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No ...

Page 27

Figure 7. CE CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE tGHEL OE CE tWS Data tRH RESET RY/BY NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates ...

Page 28

AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by DATA polling and toggle bit checking after ...

Page 29

Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM0722 START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data ...

Page 30

AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A13 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle bit ...

Page 31

Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM0722 START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO ...

Page 32

Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART P/N:PM0722 START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another NO ...

Page 33

Figure 13. TIMING WAVEFORM FOR SECTOR PROTECT/UNPROTECT VID VIH RESET SA, A6 A1, A0 Sector Protect or Sector Unprotect Data 60h 1us Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0. P/N:PM0722 Valid* ...

Page 34

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM0722 START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector address with A6=0, A1=1, ...

Page 35

Figure 15. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM0722 START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? Yes Set up first ...

Page 36

Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION A1 12V 3V A9 tVLHT A6 12V 3V OE tVLHT WE CE Data A17-A12 Notes: tWPP1 (Write pulse width for sector protect)=100ns min. tWPP2 (Write pulse width for sector unprotect)=100ns min. P/N:PM0722 tWPP ...

Page 37

Figure 17. CHIP UNPROTECTION ALGORITHM Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0722 START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 50ms Set OE=CE=VIL ...

Page 38

WRITE OPERATION STATUS Figure 18. DATA POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM0722 Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? ...

Page 39

Figure 19. TOGGLE BIT ALOGRITHM NO Program/Erase Operation Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM0722 Start Read Q7-Q0 Read Q7-Q0 ...

Page 40

Figure 20. DATA POLLING TIMINGS (DURING AUTOMATIC ALOGRITHMS) tRC Address VA tACC tCE CE tCH tOE OE tOEH WE DQ7 Q0-Q6 tBUSY RY/BY NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and ...

Page 41

Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS) tRC VA Address tACC tCE CE tCH tOE OE tOEH WE High Z Q6/Q2 tBUSY RY/BY NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...

Page 42

Table 13. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET Pulse Width (During Automatic ...

Page 43

Table 14. TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 23. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM 12V RESET 0 or Vcc ...

Page 44

Figure 25. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM0722 Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All ...

Page 45

Figure 26. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A17 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q15 ...

Page 46

Table 15. ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured ...

Page 47

... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX29LV040TC-55 55 MX29LV040TC-70 70 MX29LV040TC-90 90 MX29LV040QC-55 55 MX29LV040QC-70 70 MX29LV040QC-90 90 MX29LV040TI-70 70 MX29LV040TI-90 90 MX29LV040QI-70 70 MX29LV040QI-90 90 P/N:PM0722 OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA MX29LV040 PACKAGE 32 Pin TSOP 32 Pin TSOP ...

Page 48

PACKAGE INFORMATION 32-PIN PLASTIC LEADED CHIP CARRIER (PLCC) P/N:PM0722 MX29LV040 48 REV. 0.7, JUL. 12, 2001 ...

Page 49

PLASTIC TSOP P/N:PM0722 MX29LV040 49 REV. 0.7, JUL. 12, 2001 ...

Page 50

Revision History Revision No. Description 0.1 Added Read cycle time and Output enable hold time to READ Operation Modify Erase/Program Operation table and timing waveform Modify Program/Erase Algorithm flowchart To added write operation status 0.2 Modify Feature--10,000 minimum erase/program cycles-->100,000-- ...

Page 51

... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 51 MX29LV040 ...

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