MC14093B ON Semiconductor, MC14093B Datasheet

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MC14093B

Manufacturer Part Number
MC14093B
Description
Manufacturer
ON Semiconductor
Datasheet
MC14093B
Quad 2−Input NAND"
Schmitt Trigger
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
Symbol
V
I
The MC14093B Schmitt trigger is constructed with MOS
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
in
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Triple Diode Protection on All Inputs
Pin−for−Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt−Trigger at each Input
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
SS
DD
v (V
). Unused outputs must be left open.
in
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
(Note: Microdot may be in either location)
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G or G
http://onsemi.com
SOEIAJ−14
CASE 751A
CASE 965
CASE 948G
F SUFFIX
D SUFFIX
DT SUFFIX
TSSOP−14
SOIC−14
CASE 646
P SUFFIX
PDIP−14
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
14
1
14
14
1
1
14
DIAGRAMS
MC14093BCP
1
AWLYYWWG
MARKING
MC14093B
AWLYWW
MC14093B/D
ALYWG
14093BG
ALYW G
093B
14
G

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MC14093B Summary of contents

Page 1

... P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14093B may be used in place of the MC14011B quad 2−input NAND gate for enhanced noise immunity or to “square up” slowly changing waveforms ...

Page 2

... SS ORDERING INFORMATION Device MC14093BCP MC14093BCPG MC14093BD MC14093BDG MC14093BDR2 MC14093BDR2G MC14093BDTR2 MC14093BDTR2G MC14093BFEL MC14093BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

SWITCHING CHARACTERISTICS Î Î Î Î Î ...

Page 5

All unused inputs connected to ground −5.0 Vdc −2 −55° +25°C A −4 +125° −6.0 −10 Vdc ...

Page 6

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 7

... K D SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 8

... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE ...

Page 9

... BSC H E 7.40 8.20 0.291 0.323 0.50 0.50 0.85 0.020 0.033 L E 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 Z −−− 1.42 −−− 0.056 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC14093B/D ...

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