W88111AF Winbond, W88111AF Datasheet
W88111AF
Related parts for W88111AF
W88111AF Summary of contents
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... STAT0 - Status Register 0 - (read 0Ch) ______________________________________________________19 STAT1 - Status Register 1 - (read 0Dh) ______________________________________________________20 DHTACK - DRAM to Host Transfer Acknowledge - (write 0Eh) __________________________________21 STAT2 - Status Register 2 - (read 0Eh) ______________________________________________________21 FRST - Firmware Reset Register - (write 0Fh) ________________________________________________22 W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Table Of Contents Publication Release Date: Aug, 1996 - 1 - Preliminary/Confidential Revision A0 ...
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... MISC1 - Miscellaneous Control Register 1 (write 2Fh) _________________________________________43 MISS1 - Miscellaneous Status Register 0 - (read 2Fh) __________________________________________44 ARSTACK - ATAPI Soft Reset Acknowledge (write 30h)_________________________________________45 MISS2 - Miscellaneous Status Register 0 (read 30h)____________________________________________46 W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 2 - Preliminary/ Confidential Revision A0.1 ...
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... TMIN - Target Minute Register - (read/write 84h) _____________________________________________54 TSEC - Target Second Register - (read/write 85h) _____________________________________________54 TFRAM - Target Frame Register - (read/write 86h) ____________________________________________54 FEACTL - Feature Control Register - (write 88h)______________________________________________54 Status Mask Register - (write 8Ch-8Fh)______________________________________________________55 W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 3 - Preliminary/ Confidential Revision A0.1 ...
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... STA1M - Status 1 Mask Register - (write 8Dh) ________________________________________________55 STA2M - Status 2 Mask Register - (write 8Eh) ________________________________________________56 STA3M - Status 3 Mask Register - (write 8Fh) ________________________________________________56 REGISTER TABLE______________________________________________________________________57 D.C. CHARACTERISTICS________________________________________________________________61 PACKAGE DIMENSIONS ________________________________________________________________62 W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 4 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... The W88111AF/W88112F supports up to 1Mbytes of DRAM. It also supports ring-control-register to add flexibility of external RAM control. The host interface of W88111AF/W88112F supports data transfer using PIO, single word DMA, and multi-word DMA modes. There is an 8-byte FIFO to improve the IDE interface throughput. The W88111AF/W88112F supports multi-block-transfer from external RAM to the host. ...
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... ECC Corrector & EDC Checker Micro- Microprocessor Processor ATAPI CD-ROM Decoder & Controller External RAM Manager Subcode Interface Data FIFO 8 bytes HOST Interface Command Interface Packet FIFO 12 bytes - 6 - W88111AF/W88112F Preliminary/Confidential DRAM ATAPI Interface Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... Publication Release Date: Aug, 1996 - 7 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential GND 79 RD6 78 RD7 77 RD5 76 RD4 75 CRSTb 74 DD7 73 DD8 ...
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... PIN DESCRIPTION Microprocessor Data Bus - Bi-directional processor data lines. I Register Select - To select address register or internal register. I Microprocessor Read Strobe - A low-active signal. I Microprocessor Write Strobe - A low-active signal. I Microprocessor Chip Select - A low-active signal W88111AF/W88112F Preliminary/Confidential 5% Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... I Host I/O Read - The read strobe signal. I Host I/O Write - The write strobe signal. OZ DMA Request - A signal asserted for DMA data transfer when W88111AF/W88112F is ready to transfer data to or from the host. DA1 DA0 Control block registers 1 0 ...
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... TYPE PIN DESCRIPTION O External RAM Output Enable - External RAM read strobe. O External RAM Write Enable - External RAM write strobe W88111AF/W88112F Preliminary/Confidential Data ATAPI Features ATAPI Interrupt Reason Register Reserved for SAM TAG Bytes Drive Select ATA Command Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0 ...
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... RAM Data Bus - Data bus for external RAM. O RAM Address Bus - Address bus for external RAM. O External RAM Column Address Strobe - External RAM column address strobe. O External RAM Row Address Strobe - External RAM address strobe. Publication Release Date: Aug, 1996 - 11 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential row ...
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... Packet Command(A0h) while HIIEN(2Eh.7) is high and drive is selected. Bit 5: SRIEN - Sector Ready Interrupt Enable UINTb(pin36) is activated when SRIb(01h.5) becomes active-low if this bit is high. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 12 - Preliminary/ Confidential Revision A0 ...
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... Writing any value to register TACK(07h) deactivates this flag. Bit 5: SRIb - Sector Ready Interrupt Flag This bit is used to indicate that one sector is ready to be accessed. Reading register STAT3(0Fh) deactivates SRIb. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 13 - Preliminary/ Confidential Revision A0.1 ...
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... ISS(22h.0) becomes active-high NESBK(22h.1) becomes active-high MSS(22h.2) becomes active-high When Subcode Interrupt is activated, the microprocessor can read register SUBSTA(22h) to determine the reason of interrupt. Writing register SCIACK(22h) deactivates Subcode Interrupt. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 14 - Preliminary/ Confidential Revision A0.1 ...
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... When bit UDTS(1Fh.6) is high, the path of data transfer is from registers DF0-DF7(40h-47h) to the host. In this case, the data count, less than 8, should be set using registers TBCL(02h) before triggering THTRG and bit UDTT(1Fh.7) should be set to 1 followed by 0 after triggering THTRG. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller After one byte/word is read by host, ...
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... EIAL/EIAH are used to hold the initial address offset of the data block to be corrected. The content of BIAL/BIAH(08h/09h) will be automatically loaded to EIAL/EIAH at the beginning of each data sync, making it unnecessary to read or write EIAL/EIAH during normal operation. The RAM block for ECC is controlled by the number in registers DDBL/DDBH(28h/29h). W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 16 - Preliminary/ Confidential Revision A0 ...
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... HEAD0-3(04h-07h) and SUBH0-3(14h-17h) are retrieved from external RAM rather than from incoming serial data. When BUFEN is low, any setting of QCEN or PCEN is meaningless. Bit 1: QCEN - Q-codeword Correction Enable When this bit is high, Q-codeword RSPC correction logic is enabled. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 17 - Preliminary/ Confidential Revision A0 ...
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... ATAPI CD-ROM Decoder & Controller QCEN PCEN Decoder 0Ah.1 0Ah.0 Mode 1 1 Q-P correction 1 0 Q-correction 0 1 P-correction 0 0 Write-only 0 0 Disk-monitor X X Decoder disable Publication Release Date: Aug, 1996 - 18 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential Operation Flow Q P CRC Q CRC P CRC CRC no buffering no operation ...
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... This bit becomes high when the incoming serial data rate is too high to be processed by W88111AF/W88112F. Bit 2: SBKF - Short Block Flag If SDEN(0Bh.6) is low, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 19 - Preliminary/ Confidential Revision A0.1 ...
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... This bit is high if erasure flags are detected for both bytes in at least one subheader byte-pairs. Erasures are latched from pin C2PO if BUFEN(0Ah.2) is disabled. Otherwise, header and subheader bytes are retrieved from external RAM while the following sector is being buffered. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller SDEN Internal Operation (0Bh ...
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... This bit is high if the Form bit is high in the Submode bytes of the incoming serial data. RFORM becomes valid when flag SRIb(01h.5) becomes active-low, and remains valid until the next block sync. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 21 - Preliminary/ Confidential Revision A0 ...
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... This specification is subject to change without notice. FRST - Firmware Reset Register - (write 0Fh) Writing register FRST, regardless of what value is written, reset most of the W88111AF/W88112F logic except the followings: Register CCTL1 (1Ah) and output pin CLKO Register DSPSL (1Bh) Register HICTL1 (20h) Register SICTL0 (21h) ...
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... Read register STAT4 (10h) de-activates the above SRIb to 1. SRIb(01h.5) becomes active-low upon fast interrupt and CRC ends if FDIEN is enabled. CRCVAb should be used to determine whether CRCOK is ready when SRIb becomes active-low. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 23 - Preliminary/ Confidential Revision A0 ...
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... Bit 7-1: Reserved Bit 0: CRRL - Correction Retry Register Load Setting this bit high while writing register CRTRG (11h) re-loads the setting of EDCEN (0Ah.5), QCEN (0Ah.1), or PCEN (0Ah.0) to decoding logic. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 24 - Preliminary/ Confidential Revision A0.1 ...
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... F2RQ (0Bh.2) MCRQ (0Bh.1) FDIEN (10h.3) MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h) This register is available for W88111AF only to specify the behavior of multi-block transfer logic. The host interface supports multi-block transfer without microprocessor intervention by following sequence: MBC[4:0] the number of block to be transferred minus 1 (ex. 3) TBCL (02h), TBCH (03h) minus 1 (ex ...
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... Bit 7-2: Reserved Bit 1: IR7F - Provide Flag UTBY at IR7 When this bit is high, flag UTBY (1Fh.7) can be monitored by read bit-7 of the Index Register. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Because data count is not specified in DMA mode transfer, the Publication Release Date: Aug, 1996 - 26 - Preliminary/ Confidential Revision A0 ...
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... ATSPA (33h) 01h ATBLO (34h) 14h ATBHI (35h) EBh ATSTA (37h) 00h Note that register ATDRS (36h) is not cleared by triggering SIGT to abide by the ATAPI protocol. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 27 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... HIRQ (2Eh.3) 1 When bit PIO is low (DMA mode), this bit should not be triggered. Bit 0: SCT - Status Completion Trigger Setting this bit high triggers the following hardware sequence: W88111AF/W88112F ATAPI CD-ROM Decoder & Controller (TBCL,H+1) 2 Publication Release Date: Aug, 1996 - 28 - Preliminary/ Confidential Revision A0.1 ...
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... When the drive becomes ready after BSY is cleared, the host starts to issue 12-byte ATAPI Command Packet. Reception of the 6th packet word activates the following events. ATAPI CD-ROM Decoder & Controller 1, if AUTOEN (18h.4) is high - 29 - W88111AF/W88112F Preliminary/Confidential When APKTEN is high, the Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... PIO (1Fh.2) has been set high. STBCEN should not be set for Multiple Block Transfer. Instead, ATBLO/ATBHI should be set by firmware to: (MBKC+1) (TBCL,H+2). ATAPI CD-ROM Decoder & Controller 1, if AUTOEN (18h.4) is high - 30 - W88111AF/W88112F Preliminary/Confidential Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... PAR/JP is sampled while chip reset is active. When this bit is low, PAR/JP is sampled while chip reset or host reset are active. Bit 4: Reserved Bit 3-0: CKS[3:0] - Clock Skew Control CKS[3:0] are used to control the duty cycle of the internal clock. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 31 - Preliminary/ Confidential Revision A0.1 ...
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... Bit 0: XTALD2 - Crystal Divided by 2 The internal clock frequency is half of crystal frequency if this bit is high. VER - Version Register - (read 1Ah) This register is used to hold the version number. The current version of W88111AF is 1Bh. The current version of W88112F is 2Ah. DSPSL - DSP Selection Register - (write 1Bh) Bit 7: C2ML - C2 MSB to LSB When this bit is high, the sequence of erasures form C2PO(pin 11) is from MSB to LSB ...
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... The microprocessor should write the RAM starting address into the counter while busy flag UTBY(1Fh.7) is low. increases automatically each time when a byte is read or written. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 33 - Preliminary/ Confidential Revision A0 ...
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... Change from UDTT triggers the data transfer from DF0-DF7 to the host. This type of transfer is efficient for up to 8-byte data transfer. The host will receive data from DF0 to DF7 after the following sequence. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 34 - Preliminary/ Confidential Revision A0 ...
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... Bit 5: H16S - Host 16-bit Data Select To abide by ATAPI protocol, this bit should be high to select 16-bit data transfer between W88111AF/W88112F and host. Bit 4: LAEN - Latch Enable If this bit is high, host address and chip-select signals will be latched when pins HRDb or HWRb change from high to low ...
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... Setting this bit high causes the flag BSY in the ATAPI Status Register to become high if APKT(30h.0) is not high. Bit 2: SCoD - Select Command-Packet or Data The data received from ATAPI Data port is stored in Packet FIFO if this bit is high. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 36 - Preliminary/ Confidential Revision A0 ...
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... MSS, NESBK, or ISS if SCIEN (2CH.4) is enabled. ATAPI CD-ROM Decoder & Controller Disk Speed Subcode Block Rate 1 fold 75 sectors/sec 2 fold 150 sectors/sec 4 fold 300 sectors/sec - reserved 6 fold 450 sectors/sec 8 fold 600 sectors/sec - reserved - reserved - 37 - W88111AF/W88112F Preliminary/Confidential Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... RFC (2Ah.5) will change from when all RAM locations have been filled with the value in register RAMWR (1Eh). RFC will return to 0 when RFTRG is disabled. Bit 5: RPIEN - RAM Parity Interrupt Enable (write only) Setting this bit high enables RAM-parity-interrupt to activate pin UINTb. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 38 - Preliminary/ Confidential Revision A0 ...
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... Setting this bit high accelerates the de-assertion of IORDY without referring pin HRDb. Bit 1-0: RLC[1:0] - External RAM Layout Configuration Bits The memory layout configuration should be set as shown in the following table: ATAPI CD-ROM Decoder & Controller RAM Configuration Publication Release Date: Aug, 1996 - 39 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential ...
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... If EXOP (2Ch.2) is high, setting this bit high selects an inverted clock output at pin EXCK. Bit 2: EXOP - Pin EXCK Operation Setting this bit high sets pin EXCK as an output. ATAPI CD-ROM Decoder & Controller Data Information -- Subcode Subcode, C2 Flags Publication Release Date: Aug, 1996 - 40 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential Data Block Size reserved C00h A00h ...
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... Setting this bit high sets the drive to be selected when bit DRV in the ATAPI Drive Select Register is set to 0 (Master Drive). ATAPI CD-ROM Decoder & Controller Subcode Format SMD0 (Philips) SMD1 (EIAJ-1) SMD2 (EIAJ-2) Reserved - 41 - W88111AF/W88112F Preliminary/Confidential Publication Release Date: Aug, 1996 Preliminary/ Confidential Revision A0.1 ...
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... Bit 3: HINTF - Host Interrupt Flag This bit reflects the status of the source of pin HIRQ. Bit 2: nIEN - Bit nIEN in Device Control Register This bit reflects the value of bit nIEN in ATAPI Device Control Register. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 42 - Preliminary/ Confidential Revision A0 ...
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... Bit 0: ARWC - ATAPI Register Write Control Host writes to ATAPI registers (except Device Control Register) will not take effect when ARWC and BSY are high, if BSY is not set by the following commands: W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 43 - Preliminary/ Confidential Revision A0 ...
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... Writing 1 to CLRBSY (20h.4) Bit 5: DIAG - Execute Drive Diagnostics Command This bit becomes high if Execute Drive Diagnostics Command (opcode 90h) has been written to either master or slave drive. Meanwhile, the following events will be executed: W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 44 - Preliminary/ Confidential Revision A0 ...
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... HRST to 0. ARSTACK - ATAPI Soft Reset Acknowledge (write 30h) Writing any value to register ARSTACK triggers the following events: ATAPI CD-ROM Decoder & Controller 01h 00h 01h 01h 00h 00h Publication Release Date: Aug, 1996 - 45 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential ...
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... RPINT and the interrupt can be cleared by writing any value to register RAMCF (2Ah). Bit 2: CRST - Chip Reset Flag This bit is set high by chip reset. The first read of register MISS2 (30h) following the end of the chip reset clears CRST to 0. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 46 - Preliminary/ Confidential Revision A0 ...
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... Triggering SIGT (17h.4) ATINT - ATAPI Interrupt Reason Register (read/write 32h) This register is set as 01h by the following: Chip reset or host reset SRST Execute Drive Diagnostics Command Triggering SIGT (17h.4) W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 47 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... SRST, Execute Drive Diagnostics Command, or triggering SIGT (17h.4). Note that BSY is not changed by writing register ATSTA (37h). ATCMD - ATAPI Command Register (read 37h) This register is used to latch the command opcode written from host without default value. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 48 - Preliminary/ Confidential Revision A0 ...
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... Bit 2: ACORR - Correctable Error for Automatic Status Completion The value of ACORR is the value of bit CORR in the ATAPI Status Register during Automatic Status Completion. CORR is de-activated by chip reset, host reset, or firmware reset. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 49 - Preliminary/ Confidential Revision A0 ...
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... The microprocessor can write data to DF0-7 respectively. Then the host reads these data from ATAPI Data Register. Note that DF0 reads first, and DF7 reads last. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 50 - Preliminary/ Confidential Revision A0 ...
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... SUBCS[2:0] unless any non-zero value is written into register SCTC (5Ah). The value of register SCTC should be calculated as follows dsf = 11 where tc is the internal clock period(ex: 50nS for 20MHz crystal), dsf is the disk speed factor(ex: 4 for 4-fold speed drive). W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 51 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... Bit 6: STAERR - Status Error Flag This bit becomes high if any status bit error occurs when its corresponding mask bit enabled. It also deactivates DECEN (0AH.7) and stops the decoder automatically. deactivated by reading register TARSTA (80h). W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 52 - Preliminary/ Confidential Revision A0 ...
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... N successive sectors. Since this value is not changed by closing decoder, there is no need to write it every time before enabling the decoder. The initial value of TSL after chip reset, firmware reset and decoder reset is FFh. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 53 - Preliminary/ Confidential Revision A0 ...
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... Setting this bit high turns on the acceleration function of error correction/detection so that the system performance is highly improved. This acceleration function default for W88112F. Bit 6: ACEOFF - Acceleration Off Setting this bit low turns off the acceleration function of error correction/detection. W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 54 - Preliminary/ Confidential Revision A0 ...
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... Bit 5 - NOSYN Mask Bit 4 - LBLK Mask Bit 3 - WSHORT Mask Bit 2 - SBLK Mask Bit 0 - UCEBLK Mask STA1M - Status 1 Mask Register - (write 8Dh) Bit 4: HDERA Mask Bit 0: SHDER Mask W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 55 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... STA2M - Status 2 Mask Register - (write 8Eh) Bit 2: NOCOR Mask Bit 1: RFERA Mask STA3M - Status 3 Mask Register - (write 8Fh) Bit 5: CBLK Mask Bit 4: ECCINC Mask Bit 1: C2BLK Mask W88111AF/W88112F ATAPI CD-ROM Decoder & Controller Publication Release Date: Aug, 1996 - 56 - Preliminary/ Confidential Revision A0.1 Preliminary/Confidential ...
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... FRST 0Fh r STAT3 0 10h w CTRLW eincen 10h r STAT4 0 11h w CRTRG crrl 12h w MBTC0 mbc0 12h r MBTC0 mbc0 W88111AF/W88112F ATAPI CD-ROM Decoder & Controller BIT1 BIT2 BIT3 BIT4 index dten dfrdyb mbtib tbsyb hcib b10 b11 0 ...
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... SICTL1 scf0 2Eh w MISC0 0 2Eh r MISS0 daspb 2Fh w MISC1 arwc 2Fh r MISS1 hrst 30h w ARSTACK W88111AF/W88112F ATAPI CD-ROM Decoder & Controller mbtfen mbtien 0 0 ir7f subheader(file) subheader(channel) subheader(submode) subheader(coding) drqt adtt cpft sigt abyen 0 stbcen autoen cks1 csk2 ...
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... TARSTA hcei 81h w DSTL b0 82h w DSTH b8 81h r DSCL b0 82h r DSCH b8 83h w TSL b0 83h r TSC b0 84h r/w TMIN W88111AF/W88112F ATAPI CD-ROM Decoder & Controller fpkt crst rpint mbti eom abrt mcr ...
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... TSEC 86h r/w TFRAM 88h w FEACTL 0 8ch w STA0M uceblkm 8dh w STA1M shderam 8eh w STA2M 0 9fh w STA3M c2blkm W88111AF/W88112F ATAPI CD-ROM Decoder & Controller (bcd) (bcd sblkm wshortm lblkm hderam rferam nocorm eccincm Publication Release Date: Aug, 1996 - 60 - Preliminary/ Confidential Revision A0 ...
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... V - -133.2 -400 -133.2 -400.6 A Publication Release Date: Aug, 1996 - 61 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential CONDITION I =400 16mA (Note 1) OL UD[7:0], DD[15:0], RD[7:0], DASPb, PAR/DJ, PDIAGb, EXCK LRCK, SDATA, BCK, C2PO, SCSD, WFCK, SCSYN, HRSTb, URS, URDb, UWRb, UCSb, ...
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... This specification is subject to change without notice. ORDERING INSTRUCTION PART NO. W88111AF W88111AF-L W88111AD W88112F W88112D PACKAGE DIMENSIONS (100-pin QFP, Footprint = 4.8mm, W88111AF/W88112F 100 See Detail F y Seating Plane ATAPI CD-ROM Decoder & Controller PACKAGE FOOTPRINT (=L1X2) PQFP 100 ...
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... This specification is subject to change without notice. (100-pin QFP, Footprint = 3.9mm, W88111AF- ATAPI CD-ROM Decoder & Controller Symbol Publication Release Date: Aug, 1996 - 63 - Preliminary/ Confidential Revision A0.1 W88111AF/W88112F Preliminary/Confidential ...
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... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 - 64 - W88111AF/W88112F Preliminary/Confidential Dimension in mm Dimension in inches Symbol Min. Nom. Max. Min. Nom. Max 0.002 0.004 0.006 0.05 0.10 0.15 ...