VSC8113QB Vitesse Semiconductor Corp., VSC8113QB Datasheet
VSC8113QB
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VSC8113QB Summary of contents
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Data Sheet VSC8113 Features • Operates at Either STS-3/STM-1 (155.52Mb/s) or STS-12/STM-4 (622.08Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52MHz or 622.08MHz High Speed Clock (Mux) • On Chip Clock ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery CRU clock and data signals. (In this mode the VSC8113 operates just like the VSC8111). The receive section also contains a SONET/SDH frame detector circuit which is used ...
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Data Sheet VSC8113 Transmit Section Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN. See Figure 1. The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. TXDATAOUT ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Loss of Signal The VSC8113 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial data stream has no transition continuously for more ...
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Data Sheet VSC8113 RXDATAIN CRU Recovered Clock RXCLKIN TXDATAOUT TXCLKOUT FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) and received/recovered clock are mux’d through to the high-speed ...
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Data Sheet VSC8113 Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi- cated PLL power ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a Voltage Controlled Oscillator (VCO). The phase ...
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Data Sheet VSC8113 Jitter Tolerance Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variation in the received data stream. The bellcore and ITU specifications allow the received optical data to contain jitter. The amount that ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter ...
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Data Sheet VSC8113 Table 4: Transmit Data Input Timing Table (STS-12 Operation) Parameter T Transmit data input byte clock period CLKIN T Transmit data setup time with respect to TXLSCKIN INSU T Transmit data hold time with respect to TXLSCKIN ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 7: Receive Data Output Timing Table (STS-3 Operation) Parameter T Receive clock period RXCLKIN T Receive data output byte clock period RXLSCKT Time data on RXOUT [7:0] ...
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Data Sheet VSC8113 Data Latency The VSC8113 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock signal. Table 10: Data Latency Circuit ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 13: Clock Multiplier Unit Performance Name RCd Reference clock duty cycle RCj Reference clock jitter (RMS) @ 77.76 MHz ref RCj Reference clock jitter (RMS) @ 51.84 ...
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Data Sheet VSC8113 DC Characteristics Table 15: PECL and TTL Inputs and Outputs Parameters Description Output HIGH V OH voltage (PECL) Output LOW V OL voltage (PECL) O/P Common V Mode Range OCM (PECL) Differential V Output Voltage OUT75 (PECL) ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Power Dissipation Table 16: Power Supply Currents Parameter I Power supply current from Power dissipation (worst case) D Absolute Maximum Ratings Power Supply Voltage (V ...
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Data Sheet VSC8113 Package Pin Description Table 17: Pin Definitions Signal Pin FACLOOP 1 VDD 2 CRUEQLP 3 RESET 4 LOOPTIM0 VDDP 9 TXDATAOUT+ 10 TXDATAOUT- 11 VSS 12 TXCLKOUT+ 13 TXCLKOUT- 14 ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 17: Pin Definitions Signal Pin VDD 31 N/C 32 RX50MCK 33 VSS 34 RXOUT0 35 RXOUT1 36 VSS 37 RXOUT2 38 RXOUT3 39 VSS 40 RXOUT4 41 ...
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Data Sheet VSC8113 Table 17: Pin Definitions Signal Pin CN1 64 CN2 65 CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N CRULOCKDET VSS 75 VDD 76 N/C 77 N/C 78 N/C ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 17: Pin Definitions Signal Pin STS12 97 CRUREFSEL 98 VDD 99 EQULOOP 100 Page 20 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE ...
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Data Sheet VSC8113 Package Information PIN 100 PIN 1 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery The VSC8113 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for ...
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... VSC8113QB1 155/622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Extended Temperature ambient (equivalent ambient to 115 C case) VSC8113QB2 155Mb/s-622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Industrial Temperature, -40 C ambient case Notice This document contains information on products that are in the preproduction phase of development. The information contained in this document is based on test results and initial product characterization ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Application Notes Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8113 has been brought off-chip to allow as much flexibility in ...
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Data Sheet VSC8113 Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore the max delay is due to loading. The VSC8113 input (TXLSCKIN) plus package is about 6pf. Assuming ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance ...
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Data Sheet VSC8113 V +3 INPUT R GND REFCLK and TTL Inputs G52154-0, Rev 4.2 3/19/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock ...
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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Page 28 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 G52154-0, Rev 4.2 3/19/99 ...