S3C70F4X15-AVB4 Samsung, S3C70F4X15-AVB4 Datasheet

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S3C70F4X15-AVB4

Manufacturer Part Number
S3C70F4X15-AVB4
Description
Manufacturer
Samsung
Datasheet

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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the
same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and
its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of
general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the S3C70F2/C70F4's advanced CMOS technology provides for very
low power consumption and a wide operating voltage range — all at a very low cost.
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S3C70F4X15-AVB4 Summary of contents

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... OVERVIEW The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of general-purpose applications ...

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PRODUCT OVERVIEW FEATURES SUMMARY Memory 512 4-bit data memory (RAM) 2048 8-bit program memory (ROM):S3C70F2 4096 8-bit program memory (ROM):S3C70F4 24 I/O Pins I/O: 18 pins, including 8 high current pins Input only: 6 pins Comparator 4-channel mode: Internal reference ...

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S3C70F2/C70F4/P70F4 FUNCTION OVERVIEW SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate ...

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PRODUCT OVERVIEW DATA MEMORY Overview Data memory is organized into three areas: — 32 4-bit working registers — 224 4-bit general-purpose area in bank 0 — 256 4-bit general-purpose area in bank 1 — 128 4-bit area in bank 15 ...

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S3C70F2/C70F4/P70F4 CONTROL REGISTERS Program Status Word The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing also used to restore a program's execution environment when an interrupt has been serviced. Program instructions can always address ...

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PRODUCT OVERVIEW POWER-DOWN To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle mode; the STOP instruction initiates stop mode. In idle mode, the CPU clock stops while peripherals continue to operate normally. ...

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S3C70F2/C70F4/P70F4 BIT SEQUENTIAL CARRIER The bit sequential carrier (BSC 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions. Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs can ...

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PRODUCT OVERVIEW BLOCK DIAGRAM 8-Bit Timer/Counter P3.0/TCL0 I/O Port 3 P3.1/TCLO0 P3.2/CLO P4.0 - P4.3 I/O Port 4 I/O Port 5 P5.0 - P5.3 P6.0/KS0 P6.1/KS1 I/O Port 6 P6.2/KS2 P6.3/KS3 Figure 1-1. S3C70F2/C70F4 Simplified Block Diagram 1-8 Basic Timer ...

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S3C70F2/C70F4/P70F4 PIN ASSIGNMENTS P1.0/INT0 P1.1/INT1 RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 P1.0/INT0 P1.1/INT1 RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 Figure 1-2. S3C70F2/C70F4 Pin Assignment Diagram Xout 2 Xin 3 TEST 4 ...

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PRODUCT OVERVIEW PIN DESCRIPTIONS Pin Name Pin Type P0.0 I/O 3-bit I/O port. 1-bit or 3-bit read/write and test are P0.1 possible. Pull-up resistors are assignable to input pins by P0.2 software and are automatically disabled for output pins. Pins ...

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S3C70F2/C70F4/P70F4 Table 1-1. S3C70F2/C70F4 Pin Descriptions (Continued) Pin Name Pin Type Quasi-interrupt input with falling edge detection V — Main power supply DD V — Ground SS RESET I Reset signal Test signal input (must be connected to V TEST ...

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PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS Figure 1-3. Pin Circuit Type PULL-UP RESISTOR - P CHANNEL IN SCHMITT TRIGGER Figure 1-4. Pin Circuit Type A-3 1- CHANNEL - CHANNEL RESISTOR ENABLE S3C70F2/C70F4/P70F4 ...

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KS57C01502/C01504/P01504 RESISTOR ENABLE DATA CIRCUIT TYPE 4 OUTPUT DISABLE SCHMITT TRIGER Figure 1-7. Pin Circuit Type D-1 PNE V DD DATA - P CHANNEL - OUTPUT N CHANNEL DISABLE Figure 1-8. Pin Circuit Type PULL-UP RESISTOR - ...

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S3C70F2/C70F4/P70F4 2 ADDRESS SPACES PROGRAM MEMORY (ROM) OVERVIEW ROM maps for S3C70F2/C70F4 devices are mask programmable at the factory. In its standard configuration, the device's 4096 8-bit program memory has four areas that are directly addressable by the program counter ...

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ADDRESS SPACES GENERAL-PURPOSE MEMORY AREAS The 16-byte area at ROM locations 0010H–001FH and the 3968-byte area at ROM locations 0080H–0FFFH are used as general-purpose program memory. You can also use vacant locations in the vector address area and REF instruction ...

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S3C70F2/C70F4/P70F4 0000H Vector Address Area (16 bytes) 000FH 0010H General Purpose Area (16 bytes) 001FH 0020H Instruction Reference Area (96 bytes) 007FH 0080H S3C70F2 General Purpose Area (1,920 Bytes) 07FFH 0800H S3C70F4 General Purpose Area (3,968 Bytes) 07FFH Figure 2-1. ...

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ADDRESS SPACES + + PROGRAMMING TIP — Defining Vectored Interrupt Areas The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG 0000H ...

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S3C70F2/C70F4/P70F4 INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily refer instructions with larger byte sizes that are stored in addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations ...

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...

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S3C70F2/C70F4/P70F4 DATA MEMORY (RAM) OVERVIEW In its standard configuration, the 512 — 32 4-bit working register area — 224 4-bit general-purpose area in bank 0 (also used as stack area) — 256 4-bit general-purpose area in bank 1 — 128 ...

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ADDRESS SPACES Memory Banks 0, 1 and 15 Bank 0 (000H–0FFH) Bank 1 (100H–1FFH) Bank 15 (F80H–FFFH) Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0 or 15. When the ...

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S3C70F2/C70F4/P70F4 Table 2-2. Data Memory Organization and Addressing Addresses 000H–01FH Working registers 020H–0FFH Stack and general-purpose registers 100H–1FFH General-purpose registers F80H–FFFH I/O-mapped hardware registers + + PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1 Clear bank 0 of ...

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ADDRESS SPACES WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used ...

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S3C70F2/C70F4/P70F4 Working Register Banks For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank ...

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ADDRESS SPACES Special-Purpose Working Registers You can use register 4-bit accumulator and double register 8-bit accumulator. You can use the carry flag as a 1-bit accumulator. 8-bit double registers WX, WL and HL are ...

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S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Selecting Your Working Register Area The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 1,0,INT0 ; INT0 PUSH SB SRB 2 PUSH HL PUSH ...

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ADDRESS SPACES STACK OPERATIONS STACK POINTER (SP) The stack pointer (SP 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP ...

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S3C70F2/C70F4/P70F4 PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number determined ...

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ADDRESS SPACES POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction ...

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S3C70F2/C70F4/P70F4 BIT SEQUENTIAL CARRIER (BSC) The bit sequential carrier (BSC 16-bit register that is mapped to RAM addresses FC0H–FC3H. You can manipulate the BSC register using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit ...

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ADDRESS SPACES PROGRAM COUNTER (PC) A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC12–PC13 is reserved ...

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S3C70F2/C70F4/P70F4 INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. They are mapped to RAM bit loca- tions FB0H.2 and FB0H.3, respectively. You can manipulate IS0 and IS1 flags directly using 1-bit ...

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ADDRESS SPACES EMB FLAG (EMB) The enable memory bank flag EMB is mapped to registers FB0H–FB1H in bank 15 of the RAM. The EMB flag occupies bit location 1 in register FB0H. The EMB flag is used to allocate specific ...

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S3C70F2/C70F4/P70F4 ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", you can select the working register area from register banks according to ...

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ADDRESS SPACES SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset automatically during program execution. These flags are mapped to RAM bit locations FB1H.0, ...

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S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator 1. Set the carry flag to logic one: SCF LD EA,#0C3H LD HL,#0AAH ADC EA,HL 2. Logical-AND bit 3 of address 3FH with P3.3 and output ...

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S3C70F2/C70F4/P70F4 3 ADDRESSING MODES OVERVIEW The enable memory bank flag, EMB, controls the two addressing modes for data memory. When you enable the EMB flag, you can address the entire RAM area. When you clear the EMB flag to logic ...

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ADDRESSING MODES Addressing Mode RAM Areas 000H Working Registers 01FH 020H 07FH Bank 0 080H (General Registers and Stack) 0FFH 100H Bank 1: (General Registers ) 1FFH F80H Bank 15 (Peripheral Hardware Registers) FFFH NOTES: 1. 'X' means don't care. ...

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S3C70F2/C70F4/P70F4 EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address ...

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ADDRESSING MODES ENABLE MEMORY BANK SETTINGS EMB = "1" When you set the enable memory bank flag, EMB, to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0,1 or 15) using ...

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S3C70F2/C70F4/P70F4 SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register ...

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ADDRESSING MODES DIRECT AND INDIRECT ADDRESSING You can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit address as the instruction operand. In indirect addressing the instruction specifies a specfic register ...

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S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — 1-Bit Addressing Modes 1-Bit Direct Addressing 1. If EMB = "0": AFLAG EQU 34H.3 BFLAG EQU 85H.3 CFLAG EQU 0BAH.0 SMB 0 BITS AFLAG BITS BFLAG BTST CFLAG BITS BFLAG BITS P3 ...

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ADDRESSING MODES + + PROGRAMMING TIP — 1-Bit Addressing Modes (Continued) 1-Bit Indirect Addressing 1. If EMB = "0": AFLAG EQU 34H.3 BFLAG EQU 85H.3 CFLAG EQU 0BAH.0 SMB 0 LD H,#0BH BTSTZ @H+CFLAG BITS CFLAG ; 2. If EMB ...

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S3C70F2/C70F4/P70F4 4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Instruction Addressing Mode Notation Description DA Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection @HL Direct: 4-bit address indicated by the memory bank ...

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ADDRESSING MODES + + PROGRAMMING TIP — 4-Bit Addressing Modes (Continued) 4-Bit Indirect Addressing 1. If EMB = "0", compare bank 0, locations 040H–046H with 060H–066H: ADATA EQU 46H BDATA EQU 66H SMB 15 LD HL,#BDATA LD WX,#ADATA COMP LD ...

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S3C70F2/C70F4/P70F4 8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instructio Addressing Mode n Description Notation DA Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection @HL Indirect: the 8-bit address indicated ...

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ADDRESSING MODES + + PROGRAMMING TIP — 8-Bit Addressing Modes (Continued) 8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU 8EH LD HL,#ADATA LD EA,@ EMB = "1": ADATA EQU 46H SMB 0 LD HL,#ADATA LD ...

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S3C70F2/C70F4/P70F4 4 MEMORY MAP OVERVIEW To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of ...

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MEMORY MAP Address Register Bit 3 F80H SP F81H F82H SB F83H SMB3 F85H BMOD F86H BCNT F87H F88H WMOD F89H • • F90H TMOD0 F91H F92H F93H F94H TCNT0 F95H F96H TREF0 F97H F98H WDMOD F99H F9AH WDFLAG WDTCF ...

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S3C70F2/C70F4/P70F4 Table 4-1. I/O Map for Memory Bank 15 (Continued) Address Register Bit 3 FB8H FB9H FBAH FBBH FBCH FBDH FBEH IE1 FBFH FC0H BSC0 FC1H BSC1 FC2H BSC2 FC3H BSC3 • • FD0H CLMOD • • FD4H CMPREG FD5H ...

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MEMORY MAP Table 4-1. I/O Map for Memory Bank 15 (Concluded) Address Register Bit 3 FE2H P2MOD FE3H FE4H SBUF FE5H FE6H FE7H FE8H PMG1 FE9H FEAH PMG2 PM4.3 FEBH FECH PMG3 PM5.3 FEDH PM6.3 FEEH FEFH FF0H Port 0 ...

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S3C70F2/C70F4/P70F4 REGISTER DESCRIPTIONS In this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped I/O locations in bank 15 of the RAM. Figure 4–1 describes features of the register description format. Register descriptions ...

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MEMORY MAP Bit identifiers used for bit addressing Register ID IPR — Interrupt Priority Register Bit Identifier RESET Value RESET Read/Write Bit Addressing IME .2 – Read-only W = Write-only R/W = Read/write '–' = Not used ...

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S3C70F2/C70F4/P70F4 BMOD — Basic Timer Mode Register Bit Identifier RESET RESET Value Read/Write Bit Addressing 1/4 BMOD.3 Basic Timer Restart Bit 1 BMOD.2 – .0 Input Clock Frequency and Signal Stabilization Interval Control Bits NOTES: 1. ...

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MEMORY MAP CMOD — Comparator Mode Register Bit Identifier RESET Value RESET Read/Write R/W Bit Addressing CMOD.7 Comparator Enable/Disable Bit 0 1 CMOD.6 Conversion Time Control Bit 0 1 CMOD.5 External/Internal Reference Selection Bit 0 1 CMOD.4 Bit 4 0 ...

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S3C70F2/C70F4/P70F4 CLMOD — Clock Output Mode Register Bit Identifier RESET RESET Value Read/Write Bit Addressing CLMOD.3 Enable/Disable Clock Output Control Bit 0 1 CLMOD.2 Bit 2 0 CLMOD.1 – .0 Clock Source and Frequency Selection Control Bits ...

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MEMORY MAP IE0/1, IRQ0/1 — INT0/1 Interrupt Enable/Request Flags Bit Identifier IE1 RESET Value RESET Read/Write R/W Bit Addressing 1/4 IE1 INT1 Interrupt Enable Flag 0 1 IRQ1 INT1 Interrupt Request Flag – IE0 INT0 Interrupt Enable Flag 0 1 ...

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S3C70F2/C70F4/P70F4 IEK, IRQK — Key Interrupt Enable/Request Register Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 – .2 Bits 3–2 0 IEK Key Interrupt Request Enable Flag 0 1 IRQK Key Interrupt Request Flag – ...

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MEMORY MAP IEB, IRQB — INTB Interrupt Enable/Request Flags Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 – .2 Bits 3–2 0 IEB INTB Interrupt Enable Flag 0 1 IRQB INTB Interrupt Request Flag – 4-12 3 ...

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S3C70F2/C70F4/P70F4 IES, IRQS — INTS Interrupt Enable/Request Flags Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 – .2 Bits 3–2 0 IES INTS Interrupt Enable Flag 0 1 IRQS INTS Interrupt Request Flag – ...

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MEMORY MAP IET0, IRQT0 — INTT0 Interrupt Enable/Request Flags Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 – .2 Bits 3–2 0 IET0 INTT0 Interrupt Enable Flag 0 1 IRQT0 INTT0 Interrupt Request Flag – 4-14 3 ...

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S3C70F2/C70F4/P70F4 IEW, IRQW — INTW Interrupt Enable/Request Flags Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 – .2 Bits 3–2 0 IEW INTW Interrupt Enable Flag 0 1 IRQW INTW Interrupt Request Flag – NOTE: INTW is ...

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MEMORY MAP IMOD0 — External Interrupt 0 (INT0) Mode Register Bit Identifier RESET RESET Value Read/Write Bit Addressing IMOD0.3 Interrupt Sampling Clock Selection Bit 0 1 IMOD0.2 Bit 2 0 IMOD0.1 – .0 External Interrupt Mode Control Bits 0 0 ...

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S3C70F2/C70F4/P70F4 IMOD1 — External Interrupt 1 (INT1) Mode Register Bit Identifier "0" RESET Value RESET Read/Write Bit Addressing IMOD1.3 – .1 Bits 3–1 0 IMOD1.0 External Interrupt 1 Edge Detection Control Bit "0" "0" 0 ...

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MEMORY MAP IMODK — Key Interrupt Mode Register Bit Identifier "0" RESET Value RESET Read/Write Bit Addressing IMODK.3 Bits 3 0 IMODK.2 – .0 Key Interrupt Edge Detection Selection Bit 4-18 3 ...

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S3C70F2/C70F4/P70F4 IPR — Interrupt Priority Register Bit Identifier IME RESET RESET Value Read/Write Bit Addressing 1/4 IME Interrupt Master Enable Bit 0 1 IPR.2 – .0 Interrupt Priority Assignment Bits ...

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MEMORY MAP PCON — Clock Power Control Register Bit Identifier RESET RESET Value Read/Write Bit Addressing PCON.3 – .2 CPU Operating Mode Control Bits PCON.1 – .0 CPU Clock Frequency Selection Bits NOTE: fx ...

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S3C70F2/C70F4/P70F4 PMG1 — Port I/O Mode Flags (Group 1: Port 0, 3) Bit "0" Identifier RESET Value Read/Write Bit Addressing .7 Bit 7 0 PM3.2 P3.2 I/O Mode Selection Flag 0 1 PM3.1 P3.1 I/O Mode Selection Flag 0 1 ...

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MEMORY MAP PMG2 — Port I/O Mode Flags (Group 2: Port 4) Bit Identifier "0" RESET RESET Value Read/Write Bit Addressing .7 Bit Bit Bit Bit 4 0 PM4.3 P4.3 I/O ...

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S3C70F2/C70F4/P70F4 PMG3 — Port I/O Mode Flags (Group 3: Port 5, 6) Bit Identifier PM6.3 RESET Value RESET Read/Write Bit Addressing PM6.3 P6.3 I/O Mode Selection Flag 0 1 PM6.2 P6.2 I/O Mode Selection Flag 0 1 PM6.1 P6.1 I/O ...

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MEMORY MAP PNE — N-channel Open-drain Mode Register Bit Identifier PNE5.3 RESET RESET Value Read/Write Bit Addressing .7 P5.3 N-channel Open-drain Enable Bit P5.2 N-channel Open-drain Enable Bit P5.1 N-channel Open-drain Enable Bit 0 ...

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S3C70F2/C70F4/P70F4 PSW — Program Status Word Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing C Carry Flag 0 1 SC2 – SC0 Skip Condition Flags 0 1 IS1, IS0 Interrupt Status Flags EMB Enable Data ...

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MEMORY MAP P2MOD — Port 2 Mode Register Bit Identifier RESET RESET Value Read/Write Bit Addressing P2MOD.3 P2.3 Analog/digital Selection Bit 0 1 P2MOD.2 P2.2 Analog/digital Selection Bit 0 1 P2MOD.1 P2.1 Analog/digital Selection Bit 0 1 P2MOD.0 P2.0 Analog/digital ...

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S3C70F2/C70F4/P70F4 PUMOD — Pull-Up Register Mode Register Bit Identifier "0" RESET Value RESET Read/Write Bit Addressing .7 Bit Connect/Disconnect Port 6 Pull-Up Resistor Control Bit Connect/Disconnect Port 5 Pull-Up Resistor Control Bit 0 1 ...

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MEMORY MAP SMOD — Serial I/O Mode Register Bit Identifier RESET RESET Value Read/Write Bit Addressing SMOD.7 – .5 Serial I/O Clock Selection and SBUF R/W Status Control Bits NOTE: All kHz frequency ratings assume ...

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S3C70F2/C70F4/P70F4 TMOD0 — Timer/Counter 0 Mode Register Bit Identifier "0" RESET Value RESET Read/Write Bit Addressing .7 Bit – .4 Timer/Counter 0 Input Clock Selection Bits Clear Counter and Resume ...

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MEMORY MAP TOE0 — Timer Output Enable Flag Bit Identifier RESET RESET Value Read/Write R/W Bit Addressing 1/4 .3 Bit 3 0 TOE0 Timer/Counter 0 Output Enable Flag Bit Bit 0 0 4-30 3 ...

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S3C70F2/C70F4/P70F4 WDMOD — Watch-Dog Timer Mode Register Bit Identifier RESET Value RESET Read/Write Bit Addressing . Watch-Dog Timer Enable/Disable Control 5AH Any other value ...

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MEMORY MAP WDTCF — Watch-Dog Timer Flag Bit Identifier WDTCF RESET RESET Value Read/Write Bit Addressing .3 Watch-dog timer’s counter clear bit 1 NOTE: Instruction that clear the watch-dog timer (“BITS WDTCF”) should be executed at proper points in a ...

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S3C70F2/C70F4/P70F4 WMOD — Watch Timer Mode Register Bit Identifier RESET Value RESET Read/Write Bit Addressing WMOD.7 Enable/Disable Buzzer Output Bit 0 1 WMOD.6 Bit 6 0 WMOD.5 – .4 Output Buzzer Frequency Selection Bits WMOD.3 Bit ...

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S3C70F2/C70F4/P70F4 6 OSCILLATOR CIRCUITS OVERVIEW The S3C70F2/C70F4 has a system clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these on-chip circuits. Specifically, a clock is required by the following peripheral modules: — Basic ...

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OSCILLATOR CIRCUIT SYSTEM OSCILLATOR CIRCUIT out OSCILLATOR STOP PCON.0 PCON.1 IDLE PCON.2 STOP PCON.3 PCON.3,2 CLEAR 6-2 fx FREQUENCY DIVIDING CIRCUIT 1/2 1/16 SELECTOR OSCILLATOR CONTROL CIRCUIT Figure 6-1. Clock Circuit Diagram S3C70F2/C70F4/P70F4 WATCH TIMER BASIC TIMER ...

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S3C70F2/C70F4/P70F4 SYSTEM OSCILLATOR CIRCUITS Figure 6-2. Crystal/Ceramic Oscillator out OSCILLATOR CIRCUIT out Figure 6-3. External Clock 6-3 ...

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OSCILLATOR CIRCUIT POWER CONTROL REGISTER (PCON) The power control register, PCON 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON is mapped to RAM address FB3H and ...

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S3C70F2/C70F4/P70F4 INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided ( 64). Table 6-2 shows corresponding cycle times in microseconds. Table 6-2. Instruction Cycle ...

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OSCILLATOR CIRCUIT CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: — 4-bit clock output mode register (CLMOD) — Clock selector — Output latch — Port mode flag — ...

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S3C70F2/C70F4/P70F4 7 INTERRUPTS OVERVIEW S3C70F2/C70F4 microcontrollers process three types of interrupts: — Internal interrupts generated by on-chip processes — External interrupts generated by external peripheral devices — Quasi-interrupts used for edge detection and clock sources Table 7-1. Interrupts and Corresponding ...

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INTERRUPTS Vectored Interrupts (Continued) EMB and ERB flags for RAM memory bank and registers are stored in the vector address area of the ROM during interrupt service routines. The flags are stored at the beginning of the program with the ...

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S3C70F2/C70F4/P70F4 Generate corresponding vector interrupt IS1,0 = 0,1 Store contents of PC and PSW in the stack area; set PC contents to corresponding vector address Interrupt is generated (INT xx) Request flag (IRQx) <-- 1 NO IEx = 1? YES ...

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INTERRUPTS IMOD1 IMOD0 INT0 # @ @ INT1 INTS INTT0 INTW INTK (KS0–KS2) POWER-DOWN MODE RELEASE SIGNAL IME IS1 IS0 # = Noise filtering circuit @ = Edge detection circuit 7-4 IEK INTB IRQB IRQ0 IRQ1 IRQS IRQT0 IRQW IRQK ...

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S3C70F2/C70F4/P70F4 MULTIPLE INTERRUPTS The interrupt controller can serve multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are served multi-level interrupts, when the interrupt service routine for a ...

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INTERRUPTS Process Status Before INT IS1 – 1 Normal Program Processing (Status 0) INT Disable Set IPR INT Enable Low or High Level Interrupt Generated 7-6 Table 7-2. IS1 and IS0 Function Effect of ...

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S3C70F2/C70F4/P70F4 INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. The IPR is mapped to RAM address FB2H, and its reset value is logic zero. Before the IPR can be modified by ...

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INTERRUPTS + + PROGRAMMING TIP — Setting the INT Interrupt Priority Set the INT1 interrupt to high priority: BITS EMB SMB A,#3H LD IPR,A EI EXTERNAL INTERRUPT MODE REGISTERS (IMOD0, IMOD1) The following components are used to ...

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S3C70F2/C70F4/P70F4 EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued) When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 ma- chine cycles have elapsed. Since the INT0 pin has a ...

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INTERRUPTS KEY INTERRUPT MODE REGISTER (IMODK) The mode register for external interrupts at the KS0–KS2 pins, IMODK 4-bit register at RAM address FB6H. IMODK is addressable only by 4-bit write instructions. RESET clears all IMODK bits to logic ...

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S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Using INTK as a Key Input Interrupt When the INTK interrupt used as a key interrupt, the key interrupt pin must be set to input. 1. When KS0–KS2 are selected: BITS EMB SMB 15 ...

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INTERRUPTS INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in- terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. Interrupt Master Enable Flag (IME) The ...

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S3C70F2/C70F4/P70F4 INTERRUPT MASTER ENABLE FLAG (IME) The interrupt master enable flag, IME, inhibits or enables all interrupt processing. Therefore, even when an IRQx flag and its corresponding IEx flag is enabled, an interrupt request will not be serviced until the ...

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INTERRUPTS INTERRUPT REQUEST FLAGS (IRQx) When an interrupt request flag (IRQx) is set, a software-generated interrupt is enabled for the corresponding in- terrupt. IRQx flags can be written 4-bit RAM control instructions. IRQx flags are then cleared ...

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S3C70F2/C70F4/P70F4 8 POWER-DOWN OVERVIEW The S3C70F2/C70F4 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an ...

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POWER-DOWN Table 8-1. Hardware Operation During Power-Down Modes Operation Clock oscillator System clock oscillation stops Basic timer Basic timer stops Operates only if external SCK input is Serial interface selected as the serial I/O clock Timer/counter 0 Operates only if ...

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S3C70F2/C70F4/P70F4 IDLE MODE TIMING DIAGRAMS RESET NORMAL MODE CLOCK SIGNAL Figure 8-1. Timing When Idle Mode is Released by RESET MODE RELEASE SIGNAL NORMAL MODE CLOCK SIGNAL Figure 8-2. Timing When Idle Mode is Released by an Interrupt IDLE INSTRUCTION ...

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POWER-DOWN STOP MODE TIMING DIAGRAMS RESET NORMAL MODE CLOCK SIGNAL Figure 8-3. Timing When Stop Mode is Released by RESET MODE RELEASE SIGNAL NORMAL MODE CLOCK SIGNAL Figure 8-4. Timing When Stop Mode is Released by an Interrupt 8-4 STOP ...

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S3C70F2/C70F4/P70F4 I/O PORT PIN CONFIGURATION FOR POWER-DOWN The following method describes how to configure I/O port pins to reduce power consumption during power-down modes (stop, idle): Condition 1: If the microcontroller is not configured to an external device: 1. Connect ...

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POWER-DOWN RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2. Table 8-2. Unused Pin Connections for Reducing Power Consumption Pin/Share Pin Names P0.0/SCK P0.1/SO P0.2/SI P1.0/INT0 – ...

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S3C70F2/C70F4/P70F4 9 RESET RESET OVERVIEW When a RESET signal is input during normal operation or power-down mode, a reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31 4.19 ...

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RESET Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent Program counter (PC) Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Stack pointer (SP) Data Memory ...

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S3C70F2/C70F4/P70F4 Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD) Port 2 mode register (P2MOD) N-channel open-drain mode register (PNE) Watch-dog Timer: WDT ...

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S3C70F2/C70F4/P70F4 10 I/O PORTS OVERVIEW The S3C70F2/C70F4 has 2 input ports and 5 I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FF6H in bank 15 of the RAM. The contents of I/O port pin latches can ...

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I/O PORTS Port I/O Pins I/O 4 Table 10-2. I/O Port Pin Status During Instruction Execution Instruction Type Example 1-bit test BTST P0.1 ...

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S3C70F2/C70F4/P70F4 PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports 0 and 3–6 to input or output mode by setting or clearing the corresponding I/O buffer. PM flags are stored in three 8-bit registers ...

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I/O PORTS PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used either for analog input or for digital input. P2MOD register is 4-bit write only register. P2MOD is mapped to address FE2H and initialized to ...

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S3C70F2/C70F4/P70F4 PORT 0 CIRCUIT DIAGRAM SMOD.7 SMOD.6 SMOD.5 PUMOD.0 PUMOD.0 PUMOD.0 P0.0 / SCK P0 P0 When a port pin acts as an output, its pull-up resistor is automatically disabled, NOTE: even though the port's pull-up ...

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I/O PORTS PORT 1 CIRCUIT DIAGRAM PUMOD.1 P1.0 / INT0 P1.1 / INT1 N/R = Noise reduction 10 Figure 10-2. Input Port 1 Circuit Diagram S3C70F2/C70F4/P70F4 INT0 INT1 IMOD0 N/R Circuit ...

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S3C70F2/C70F4/P70F4 PORT 2 CIRCUIT DIAGRAM P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 Figure 10-3. Port 2 Circuit Diagram I/O PORTS DIGITAL INPUT ANALOG INPUT DIGITAL INPUT ANALOG INPUT DIGITAL INPUT ANALOG INPUT DIGITAL INPUT ANALOG ...

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I/O PORTS PORT 3 CIRCUIT DIAGRAM PUMOD.3 PUMOD.3 PUMOD.3 P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO When a port pin acts as an output, its pull-up resistor is automatically disabled, NOTE: even though the port's pull-up resistor is ...

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S3C70F2/C70F4/P70F4 PORTS 4 AND 5 CIRCUIT DIAGRAM V DD P-CH P-CH Px.b N- Figure 10-5. Circuit Diagram for Port 4 and 5 I/O PORTS b= PUMOD.b 8 PNE OUTPUT LATCH 8 PMx.b x=4, ...

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I/O PORTS PORT 6 CIRCUIT DIAGRAM PUMOD.6 PUMOD.6 PUMOD.6 PUMOD.6 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / BUZ When a port pin acts as an output, its pull-up resistor is automatically disabled, NOTE: even though the ...

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S3C70F2/C70F4/P70F4 11 TIMERS and TIMER/COUNTERS OVERVIEW There are three timer and timer/counter function modules: — 8-bit basic timer (BT) — 8-bit timer/counter 0 (TC0) — Watch timer (WT) The 8-bit basic timer (BT) is the microcontroller's main interval timer. It ...

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TIMERS and TIMER/COUNTERS BASIC TIMER (BT) OVERVIEW The 8-bit basic timer (BT) has five functional components: — Clock selector logic — 4-bit mode register (BMOD) — 8-bit counter register (BCNT) — Watchdog timer control register (WDMOD) — Watchdog timer clear ...

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S3C70F2/C70F4/P70F4 Register Type Name BMOD Control Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or RESET BCNT Counter Counts clock pulses matching the BMOD frequency setting WDMOD Control Controls watch-dog ...

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TIMERS and TIMER/COUNTERS BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD 4-bit write-only register located at RAM address F85H. Bit 3, the basic timer start control bit, is also 1-bit addressable. All BMOD values are ...

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S3C70F2/C70F4/P70F4 BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter register for the basic timer mapped to RAM addresses F86H–F87H and can be addressed by 8-bit read instructions. RESET leaves the BCNT register value undetermined. BCNT is automatically ...

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TIMERS and TIMER/COUNTERS + + PROGRAMMING TIP — Using the Basic Timer 1. To read the basic timer count register (BCNT): BITS EMB SMB 15 BCNTR LD EA,BCNT LD YZ,EA LD EA,BCNT CPSE EA,YZ JR BCNTR 2. When stop mode ...

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S3C70F2/C70F4/P70F4 WATCH-DOG TIMER MODE REGISTER (WDMOD) The watch-dog timer mode register, WDMOD 8-bit write-only register located at RAM address F98H - F99H. WDMOD register controls to enable or disable the watch-dog timer function. WDMOD values are set to ...

Page 128

TIMERS and TIMER/COUNTERS 8-BIT TIMER/COUNTER 0 (TC0) Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time ...

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S3C70F2/C70F4/P70F4 TC0 COMPONENT SUMMARY Mode register (TMOD0) Reference register (TREF0) Counter register (TCNT0) Clock selector circuit 8-bit comparator Output latch (TOL0) Output enable flag (TOE0) Interrupt request flag (IRQT0) This flag is cleared when TC0 operation starts and the TC0 ...

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TIMERS and TIMER/COUNTERS P3.0 TCL0 TMOD0.7 TMOD0.6 TMOD0.5 8 TMOD0.4 TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 TCLO0 PM3.1 TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 — Set TMOD.2 to logic one (RAM address F90H.2) — Set the TC0 interrupt enable flag IET0 to ...

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S3C70F2/C70F4/P70F4 TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system clock frequency you select. The 8-bit TC0 mode register, TMOD0, is used to activate the timer/counter 0 and to ...

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TIMERS and TIMER/COUNTERS TC0 EVENT COUNTER FUNCTION Timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the TCL0 pin (I/O port 3.0) as the counter source. The TC0 mode register is ...

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S3C70F2/C70F4/P70F4 TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To select the clock frequency, you load appropriate values to the TC0 mode register, TMOD0. The clock interval ...

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TIMERS and TIMER/COUNTERS TC0 SERIAL I/O CLOCK GENERATION Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn ...

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S3C70F2/C70F4/P70F4 TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter located at RAM addresses F90H–F91H and is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writable. RESET clears all TMOD0 ...

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TIMERS and TIMER/COUNTERS Table 11-7. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings TMOD0.6 TMOD0 NOTE: 'fx' = system clock + + PROGRAMMING TIP — Restarting TC0 Counting Operation 1. ...

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S3C70F2/C70F4/P70F4 TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is mapped to RAM addresses F94H–F95H read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero ...

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TIMERS and TIMER/COUNTERS TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register that is mapped to RAM locations F96H and F97H addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to ...

Page 139

S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Setting a TC0 Timer Interval To set timer interval for TC0, given fx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time ...

Page 140

TIMERS and TIMER/COUNTERS WATCH TIMER OVERVIEW The watch timer is a multi-purpose timer consisting of three basic components: — 8-bit watch timer mode register (WMOD) — Clock selector — Frequency divider circuit Watch timer functions include real-time and watch-time measurement ...

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S3C70F2/C70F4/P70F4 WATCH TIMER CIRCUIT WMOD.7 0 WMOD.5 8 WMOD.4 0 ENABLE / DISABLE WMOD.2 WMOD.1 0 P6.3 LATCH MUX fw/16 (2 KHz) fw/8 (4 kHz) FREQUENCY fw CLOCK DIVIDING 32.768 kHz SELECTOR CIRCUIT GND fx/128 Figure 11-4. Watch Timer Circuit ...

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TIMERS and TIMER/COUNTERS WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations mapped to RAM lo- cations F88H–F89H and is 8-bit write-only addressable. RESET sets all WMOD bits ...

Page 143

S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Using the Watch Timer 1. Select a 0.5 second interrupt, and 2 kHz buzzer enable: BITS EMB SMB 15 LD EA,#80H LD PMG3,EA BITR P6.3 LD EA,#84H LD WMOD,EA BITS IEW 2. Sample real-time ...

Page 144

S3C70F2/C70F4/P70F4 12 COMPARATOR OVERVIEW Port 2 can be used as a analog input port for a comparator. The reference voltage for the 4-channel comparator can be supplied either internally or externally at P2.3. When internal reference voltage is used, four ...

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COMPARATOR P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 (EXTERNAL 1/ 1/2R 12 – REF REF (INTERNAL) Figure 12-1. Comparator ...

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S3C70F2/C70F4/P70F4 COMPARATOR MODE REGISTER (CMOD) The comparator mode register CMOD is an 8-bit register that is used to set the operation mode of the comparator mapped to addresses FD6H–FD7H and can be manipulated using 8-bit memory instructions. Based ...

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COMPARATOR PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used for analog or digital input. The P2MOD register is 4-bit write only register. P2MOD is mapped to address FE2H and initialized to logic zero by ...

Page 148

S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Programming the Comparator The following code converts the analog voltage input at CIN0–CIN3 pins into 4-bit digital code. BITR EMB LD A,#00H LD P2MOD,A LD EA,#0CXH LD CMOD,EA WAIT0 LD L,#1H WAIT1 LD W,A ...

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S3C70F2/C70F4/P70F4 13 SERIAL I/O INTERFACE OVERVIEW The serial I/O interface (SIO) has the following functional components: — 8-bit mode register (SMOD) — Clock selector circuit — 8-bit buffer register (SBUF) — 3-bit serial clock counter Using the serial I/O interface, ...

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SERIAL I/O INTERFACE SIO OPERATION SEQUENCE The general sequence of operations for the serial I/O interface may be summarized as follows: 1. Set SIO mode to transmit-and-receive or to receive-only. 2. Select MSB-first or LSB-first transmission mode. 3. Set the ...

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S3C70F2/C70F4/P70F4 SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register, SMOD 8-bit register that specifies the operation mode of the serial interface. SMOD is mapped to RAM address FE0H–FE1H and its reset value is logic zero. SMOD ...

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SERIAL I/O INTERFACE SERIAL I/O TIMING DIAGRAMS SCK DI7 SI DO7 SO IRQS SET SMOD.3 Figure 13-2. SIO Timing in Transmit/Receive Mode SCK DI7 SI SO IRQS SET SMOD.3 13-4 DI6 DI5 DI4 DO6 DO5 DO4 DI6 DI5 DI4 HIGH ...

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S3C70F2/C70F4/P70F4 SERIAL I/O BUFFER REGISTER (SBUF) When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer register are output to the SO pin (P0.1) at the rate of one bit for each falling ...

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SERIAL I/O INTERFACE + + PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued) 3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode: BITS EMB SMB 15 LD EA,#03H LD PMG1,EA ...

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S3C70F2/C70F4/P70F4 + + PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued) 4. Transmit and receive an external clock in LSB-first mode: BITS EMB SMB 15 LD EA,#02H LD PMG1,EA LD EA,TDATA LD SBUF,EA LD EA,#0FH LD SMOD,EA EI ...

Page 156

SERIAL I/O INTERFACE + + PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Concluded) Use CPU clock to transfer and receive serial data at high speed: BITS EMB SMB 15 LD EA,#03H LD PMG1,EA LD EA,TDATA LD SBUF,EA LD ...

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S3C70F2/C70F4/P70F4 14 ELECTRICAL DATA ( Parameter Symbol Supply Voltage Input Voltage Output Voltage Output Current High Output Current Low Operating Temperature Storage Temperature (T = – Parameter ...

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ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued – Parameter Symbol V V Output Low OL Voltage I OL Ports All output pins except ...

Page 159

S3C70F2/C70F4/P70F4 Table 14-2. D.C. Electrical Characteristics (Concluded – Parameter Symbol I Supply Run mode; V DD1 (1) Crystal oscillator; C1=C2=22pF Current Idle mode; V DD2 Crystal ...

Page 160

ELECTRICAL DATA (T = – 1 5 Oscillator Clock Configuration Ceramic Xin Xout Oscillator C1 C2 Crystal Xin Xout Oscillator C1 C2 External Xin Xout Clock NOTES: 1. ...

Page 161

S3C70F2/C70F4/P70F4 ( Parameter Symbol C Input IN Capacitance C Output OUT Capacitance C I/O Capacitance IO Table 14-5. Comparator Electrical Characteristics (T = – ...

Page 162

ELECTRICAL DATA Table 14-6. A.C. Electrical Characteristics ( Concluded – Parameter Symbol SCK High, Low Width t SI Setup Time to SIK SCK High ...

Page 163

S3C70F2/C70F4/P70F4 Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (T = – Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait (1) time NOTES: ...

Page 164

ELECTRICAL DATA V DD EXECUTION OF STOP INSTRUCTION POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request Figure 14-4. A.C. Timing Measurement Points (Except for X Xin 14-8 STOP MODE DATA RETENTION ...

Page 165

S3C70F2/C70F4/P70F4 TCL RESET INT0, 1 KS0 to KS2 TIL Figure 14-6. TCL Timing t RSL Figure 14-7. Input Timing for RESET t INTL 0.8 VDD 0.2 VDD Figure 14-8. Input Timing for External Interrupts ELECTRICAL ...

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ELECTRICAL DATA SCK 14-10 t CKY SIK INPUT DATA KSO OUTPUT DATA Figure 14-9. Serial Data Transfer Timing S3C70F2/C70F4/P70F4 0 0 KSI V 0 0.2 ...

Page 167

... S3C70F2/C70F4/P70F4 15 MECHANICAL DATA OVERVIEW The S3C70F2/C70F4/P70F4microcontroller is available in a 30-pin SDIP package (Samsung part number 30- SDIP-400) and a 32-SOP package (Samsung part number 30-SOP-450A). #30 #1 (1.30) NOTE: Dimensions are in millimeters. 30-SDIP-400 27.88 MAX 27.48 ± 0.20 0.56 ± 0.10 1.12 ± 0.10 Figure 15-1. 30-SDIP-400 Package Dimensions MECHANICAL DATA #16 #15 1.778 0-15 15-1 ...

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MECHANICAL DATA #32 #1 (0.43) NOTE: Dimensions are in millimeters. 15-2 32-SOP-450A 20.30 MAX 19.90 0.20 0.40 0.10 Figure 15-2. 30-SOP-450A Package Dimensions S3C70F2/C70F4/P70F4 0-8 #17 + 0.10 #16 0.25 - 0.05 0.10 MAX 1.27 ...

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S3C70F2/C70F4/P70F4 16 S3P70F4 OTP OVERVIEW The S3P70F4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C70F2/C70F4 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The ...

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S3P70F4 OTP /TEST PP P1.0/INT0 P1.1/INT1 RESET /RESET RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 NOTE: Figure 16-2. S3P70F4 Pin Assignments (32-SOP Package) 16 Xout 2 Xin ...

Page 171

S3C70F2/C70F4/P70F4 Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name Pin Name P6.2 SDAT P6.3 SCLK V (TEST) TEST PP RESET RESET NOTE ...

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S3P70F4 OTP OTP ELECTRICAL DATA ( Parameter Symbol Supply Voltage Input Voltage Output Voltage Output Current High Output Current Low Operating Temperature Storage Temperature (T = – ...

Page 173

S3C70F2/C70F4/P70F4 Table 16-5. D.C. Electrical Characteristics (Continued – Parameter Symbol V V Output Low OL Voltage I OL Ports All output pins except Ports ...

Page 174

S3P70F4 OTP Table 16-5. D.C. Electrical Characteristics (Concluded – Parameter Symbol I Supply Run mode; V DD1 (1) Current Crystal oscillator; C1=C2=22pF Idle mode; V DD2 ...

Page 175

S3C70F2/C70F4/P70F4 (T = – 2 5 Oscillator Clock Configuration Ceramic Oscillation frequency Xin Xout Oscillator C1 C2 Stabilization time Crystal Oscillation frequency Xin Xout Oscillator C1 C2 Stabilization ...

Page 176

S3P70F4 OTP ( Parameter Symbol C Input IN Capacitance C Output OUT Capacitance C I/O Capacitance IO Table 16-8. Comparator Electrical Characteristics (T = – ...

Page 177

S3C70F2/C70F4/P70F4 Table 16-9. A.C. Electrical Characteristics ( Concluded – Parameter Symbol SCK High, Low Width t SI Setup Time to SIK SCK High t ...

Page 178

S3P70F4 OTP Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (T = – Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait (1) time ...

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S3C70F2/C70F4/P70F4 FAIL Verify Byte Device Failed START Address= First Location V =5V, V =12. Program One 1ms Pulse Increment X YES Verify 1 Byte Last Address ...

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