MDS212CG Zarlink Semiconductor, MDS212CG Datasheet
MDS212CG
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MDS212CG Summary of contents
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... SRAM Figure 10/100Mbps Port System Configuration Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. MDS212CG • ID Tagging Insertion/Extraction • Supports IP Multicasting through IGMP Snooping • XpressFlow Quality of Service (QoS), IEEE 802 ...
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... The MDS212 is fabricated with 2.5 V technology, where the inputs are 3.3V tolerant and the outputs are capable of directly interfacing to Low-Voltage TTL levels. The MDS212 is packaged in a 456-pin Ball Grid Array. MDS212 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The LED interface has 3 output signals (1 data and 2 control). The XPipe is 32-bits wide. MDS212 32 Registers 64 32 Search Engine 64 64 Frame Engine RMII Figure 2 - System Block Diagram 3 Zarlink Semiconductor Inc. Data Sheet TM HISC 32 Reduced Xpipe 3.2Gbps Engine XpressFlow Pipe 64 32 LED Xface ...
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... Send And Receive Frames For Management CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 Communication Between HISC and Switching Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.1 Communication Between Search Engine And HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.2 Communication Between HISC and Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5 Communication Between Management CPU and HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5.1 CPU-HISC Communication Using Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MDS212 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.1.1 Physical Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.2 Setting Register For Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.2.1 APMR- Port Mirroring Register 14.0 Virtual Local Area Networks (VLAN 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14.2 VLAN Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2.1 Static Definitions Of VLAN Membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2.2 Dynamic Learning Of VLAN Membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2.3 Dynamic Learning Of Remote VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 MDS212 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... FCBST - FCB QUEUE - Buffer Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.2.4.3 BCT - (FCB) Buffer Counter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.4.4 BCHL - Buffer Counter Hi-low Selection 18.2.5 Queue Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.5.1 CINQ - CPU Input Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.5.2 COTQ - CPU Output Queue 18.2.6 Switching Control Register 18.2.6.1 HPCR - HISC Processor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 MDS212 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... CPUIRDAT - CPU Internal RAM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.11.11 LEDR - LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.12 Ethernet MAC Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.12.1 ECR0 - MAC Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.12.2 ECR1 - MAC Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.12.3 ECR2 - MAC Port Interrupt Mask Register MDS212 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... ECR3 - MAC Port Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 18.2.12.5 ECR4 - Port Status Counter Wrapped Signal 18.2.12.6 PVID Register 100 19.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 19.1 Absolute Maximum Ratings 101 19.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.0 AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.1 XPIPE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.3 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 MDS212 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 30 - Port Mirroring Interface - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 32 - Reduce Media Independent Interface - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 33 - LED Interface - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 MDS212 List of Figures 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Table Characteristics - CPU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table Characteristics - Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table Characteristics - Port Mirroring Interface 108 Table Characteristics - Reduced Media Independent Interfac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MDS212 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...
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... M6_R M7_T M7_R M8_T M8_R M9_C RXD XD0 XD0 XD0 XD0 XD1 XD0 RS_ Zarlink Semiconductor Inc. Data Sheet X_DI X_DI X_DI X_DI X_DI X_DI X_DI P_CS ...
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... L_D46 U4 L_D47 U5 L_D48 V3 L_D49 W1 L_D50 W2 L_D51 V4 L_D52 W3 L_D53 Y1 L_D54 Y2 L_D55 Y3 L_D56 W4 L_D57 W5 12 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. L_D58 AA1 L_D59 AA2 L_D60 AA3 L_D61 Y4 L_D62 AB1 L_D63 AB2 M0_LNK AC1 M_CLKI AA4 M0_TXEN AB3 M0_TXD1 AC2 M3_TXD1 ...
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... T_D14 V25 T_D13 V26 T_D12 U24 T_D11 U25 T_D10 R22 T_D9 T23 T_D8 U26 T_D7 T24 T_D6 T25 13 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. T_D5 T26 T_D4/BS_RDYOP R23 T_D3/BS_PSD R24 T_D2/BS_SWM R25 T_D1/BS_RW R26 T_D0/BS_BMOD P23 P_D0 P22 P_D1 ...
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... X_DI3 B22 X_DI4 A22 X_DI5 D20 X_DI6 C21 X_DI7 B21 X_DI8 A21 X_DI9 D19 X_DI10 C20 X_DI11 B20 14 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. X_DI12 A20 X_DI13 E17 X_DI14 C19 X_DI15 D18 X_DI16 B19 X_DI17 A19 X_DI18 C18 X_DI19 ...
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... D5 L_A17 C4 L_A18 B3 L_A19 A3 L_A20 A2 RESERVED B2 VCC E7 VCC E11 VCC E16 VCC E20 VCC G5 VCC G22 15 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. VCC L5 VCC L22 VCC T5 VCC T22 M_MDC AB23 LE_DI AC25 LE_CLKO AB24 LE_SYNCI AA23 LE_DO AC26 LE_SYNCO AB25 ...
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... MDS212 Ball Signal Name No. GND P16 GND R11 GND R12 GND R13 GND R14 GND R15 GND R16 GND T11 GND T12 GND T13 GND T14 GND T15 GND T16 GND AB5 GND AB14 GND AB22 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Bus Grant to CPU - Only using in debug mode when system in unmanaged. Input/Output Bus Request from secondary MDS212 to primary MDS212. Only using in debug mode when system in unmanaged. Input/Output Bus Grant to secondary MDS212 from primary MDS212. Only using in debug mode when system is unmanaged. 17 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Frame Buffer Write Chip Select [1:0] Output Frame Buffer Read Chip Select [1:0] Output MII Management Data Clock – (Common for all RMII Ports[11:0]) IO-TS MII Management Data I/O – (Common for all RMII Ports{11:0]) Input Reference Input Clock 18 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Input- ST, U Ports [11:0] -- Link Status Input XpipeFlow Data Clock Input Input XpipeFlow Data Enable Input Input XpipeFlow Flow Control Input Input XpipeFlow Data Input Bits [31:0] Output XpipeFlow Data Clock Output Output XpipeFlow Flow Control Output 19 Zarlink Semiconductor Inc. Data Sheet Description ...
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... LED Serial Data Input Stream Input, U LED Input Data Stream Envelop Output LED Serial Interface Output Clock Output LED Serial Data Output Stream Output LED Output Data Stream Envelop Input System Clock at 100 MHz Power +2.5 Volt DC Supply 20 Zarlink Semiconductor Inc. Data Sheet Description ...
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... CPU Read/Write Control Polarity Selection Default=1 0=R/W#; Input Switch mode: Default=1 0=Managed mode Input Primary Device Enable Pin Default=1 0=Secondary Input Option of merge the P_RDY# and P_BRDY# as one pin Default=1 0=Merged pin 21 Zarlink Semiconductor Inc. Data Sheet Description 1=W/R# 1= Unmanaged 1=Primary 1=Separated pins ...
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... This jam sequence will persist for 32 bit times. The jam sequence bit predetermined pattern used to notify others of a collision on the network collision occurs during preamble generation, or within the first 64 bytes, the transmitter waits until the preamble is completed and then “backs off” MDS212 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Collision-based Flow Control, also referred to as Backpressure Flow Control, inhibits frame reception for ports operating in half-duplex mode by “jamming” the link. When the free buffer space drops below a user-defined buffer memory threshold, the MDS212 sends a jam sequence to all non transmitting ports, after approximately eight bytes MDS212 23 Zarlink Semiconductor Inc. Data Sheet ...
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... For local destination ports, the Frame Engine writes a job to each port’s TxQ. When a transmission job is selected, the TxDMA moves data from the memory to the MAC TxFIFO. Multicast frame data is sent multiple times, until all local destination ports’ requests are satisfied. MDS212 24 Zarlink Semiconductor Inc. Data Sheet ...
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... Free handles point to buffers that are not occupied by a frame. These free buffers can be allocated to a new frame received by the RxDMA or the MRP. When the Frame Engine is done processing a frame, its handle is released to the free handle pool. MDS212 25 Zarlink Semiconductor Inc. Data Sheet ...
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... The following figure shows the connections between the Frame Buffer Memory and the MDS212 for one-bank and two-bank memory configurations: MDS212 One Bank Size ½MB 1MB Table 1 - Type and Size of Memory Chips 26 Zarlink Semiconductor Inc. Data Sheet Two Bank Address Size L_A[19:3] 1M L_A[20:3] 2M ...
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... K bytes to 1.5M bytes 48 (4 level 24 Kbytes to 192Kbytes priority) (at 4 level priority) 128 bytes to 32 Kbytes (at 32 Bytes each Kbytes 1 16 Kbytes to 64 Kbytes 27 Zarlink Semiconductor Inc. Data Sheet L_D[31:0] L_D[31:0] CE L_A[18:3] MDS212 L_A[19] L_D[63:32] L_D[63:32] Two Bank 1M 64Kx32 L_D[31:0] ...
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... Note: The FDB must start at location 0. MDS212 Unit Count Total Size 256 to 1K 384 K bytes to 1.5M bytes 48 (4 level 24 Kbytes to 192Kbytes (at priority) 4 level priority level priority) 128 bytes to 32 Kbytes (at 32 Bytes each) 28 Zarlink Semiconductor Inc. Data Sheet Reference HISC & SE ...
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... Byte Byte Byte Byte Byte Byte Figure 4 - Memory Map of Managed System 29 Zarlink Semiconductor Inc. Data Sheet 0 0 Programmable Size Programmable Size 32KB 16 64KB MAX Byte Byte 1/2MB, 1MB or 2MB 1 0 ...
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... Queue = 128 to 1K) HISC Mailing List (# entry = 128 to 1K) (each mail entry = 32 bytes to 64 bytes) Byte Byte Byte Byte Byte Byte Byte Zarlink Semiconductor Inc. Data Sheet 0 0 Programmable Size Programmable Size MAX Byte 1/2MB, 1MB or 2MB 0 ...
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... Options + Padding Sequence Number Acknowledgement Number Reserved Checksum Urgent Pointer Options + Padding Data Figure 6 - Typical Packet Header Information 31 Zarlink Semiconductor Inc. Data Sheet EFD Packet Source MAC Address Total Length Fragment Offset Header Checksum Destination Port # Window 64 Bytes ...
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... When two MDS212 chips are connected, and configured to operate with synchronized MCT entries, the HISC processor has the ability to send a request to the Search Engine, instructing it to learn a new address received from MDS212 32 Zarlink Semiconductor Inc. Data Sheet ...
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... IP Multicast The Search Engine supports the ability of the MDS212 to provide IP Multicast by identifying Internet Group Multicast Protocol (IGMP) packets when parsing the packet header information provided by the Frame Engine. MDS212 33 Zarlink Semiconductor Inc. Data Sheet ...
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... Requests from the switching hardware (Search Engine) • Real time clock • Interrupts to the management CPU The HISC performs the following major operations: • Resource initialization • Resource management • Switching database management • Send and receive frames for management CPU MDS212 34 Zarlink Semiconductor Inc. Data Sheet ...
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... Whenever a packet-forwarding request is received from the management CPU, the HISC forwards the request to the Frame Engine via the FIFO. To alleviate the workload of the management CPU, certain management packets can be processed by the HISC, and then forwarded to the Frame Engine for transmission via the FIFO. MDS212 35 Zarlink Semiconductor Inc. Data Sheet ...
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... When a mail message arrives from the HISC, the mailbox hardware sends an interrupt, namely “Mail Arrive” (MAIL_ARR), to the CPU. The CPU can then access the mail via the Mailbox Access Register (AMBX). At this point, the CPU reads the mail handle and retrieves the contents of the mail from the AMBX Register. MDS212 36 Zarlink Semiconductor Inc. Data Sheet ...
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... The timing relationship between the data, clock, and data enable signals are described in the XPipe Timing (section Section 8.2 “XPipe Timing” ”). MDS212 X_DI[31:0] X_DO[31:0] X_DCLKI X_DCLKO X_DENI X_DENO X_DO[31:0] X_DI[31:0] X_DCLKO X_DCLKI X_DENI X_FCO 37 Zarlink Semiconductor Inc. Data Sheet Receive FIFO X_FCO Recd Ctrl Transmit FIFO X_DENO X_FCI Xmit Source Ctrl MDS212 Target ...
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... Transmit Data Enable - Provided by the source end to envelop the entire XPipe message. Flow Control Signal - A flow control pin from the target end to signal the source end to active XON/XOFF. 0-64 Words Payload Data Payload Figure 8 - XPipe Message Header 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Physical Layer (Phy) Interface The Physical Layer Interface is designed to interface Zarlink Semiconductor chipsets to a variety of Physical Layer devices. Reduced Media Independent Interface (RMII) is used for 10/100 interfaces. The chip ball names for the MAC use M as the first letter of the name, followed by their pin number, and then their function. M1_RXD0 refers to Mac port 1, receive data 0, of the receive data pair ...
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... Input Receive Data Output Transmit Enable Output Transmit Data Input (Not required) Receive Error Table 5 - RMII Specification Signals Control Bus MDS212 CPU Control Bus Secondary DEV MDS212 40 Zarlink Semiconductor Inc. Data Sheet Direction (with respect to the MAC) Flash Memory Flash Memory ...
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... Primary Device Enable (only in Unmanaged Mode) 0=Secondary Mode 1=Primary Mode (The arbiter is activated in the chip with Primary Device.) 1 Option of merger the P_RDY# and P_BRDY# 1=Seperated P_RDY# and P_BRDY# pins 0=merged P_RDY# and P_BRDY# pin Table 6 - Bootstrapping Options 41 Zarlink Semiconductor Inc. Data Sheet ...
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... At most, three devices, two MDS212 devices and one CPU, can operate on the CPU Interface at the same time. MDS212 Write cycle Read cycle wait Read wait Read cycle = 8 clks 42 Zarlink Semiconductor Inc. Data Sheet Sample Burst wait Read Read Read Read ...
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... Figure 13 - Block Diagram of the Arbiter Bit[1] must be ‘0’ for register of MWARS, MRARS, MWARB, MRARB Bit[1] must be ‘1’ for register of MWARS, MRARS, MWARB, MRARB 43 Zarlink Semiconductor Inc. Data Sheet MDS212 Secondary Master the State Machine No byte swapping for CPU data ...
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... MDS212 Byte 1 Byte Byte 3 Byte 2 Figure example of byte swapping LE_CLKO MDS212 Slave LE_SYNCO LE_SYNCI LE_DO LE_DI Figure 15 - LED Interface Connections 44 Zarlink Semiconductor Inc. Data Sheet Byte 2 Byte Byte 1 Byte 0 LED Decoder LED Display ...
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... A synchronous pulse--defines the boundary between frames. The length of each LED data frame is about 256-bits that shift out by LED_CLK per bit. A continuous serial stream of data for all status LEDs which repeat once every frame time. 45 Zarlink Semiconductor Inc. Data Sheet ...
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... Frame Engine, after receiving this DATA_FWD_REQ message, will place a job in the Transmission Scheduling queue of the destination port. MDS212 One Frame 256x80nsec Cycle #3 Cycle #4 Cycle #5 bit 2 bit 3 bit 4 bit 5 Figure 16 - Time Diagram of LED Interface 46 Zarlink Semiconductor Inc. Data Sheet Slave dev sub-frame 16 slots Cycle #6 Cycle #7 Cycle #8 Cycle #9 P1 bit 6 bit 7 bit 0 bit 1 ...
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... When the destination port is ready to send the frame, the destination Frame Engine send a Data Request message to the source Frame Engine. • After the source Frame Engine receives the Data Request Message, it starts to move the frame in granule form, which is directly written in the destination TxFIFO. MDS212 47 Zarlink Semiconductor Inc. Data Sheet ...
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... MDS212. After reading the frame from the FDB, the CPU will inform the HISC to release the FDB. Finally, the HISC passes the release command to the Frame Engine to release the FDB accommodated CPU frame. MDS212 48 Zarlink Semiconductor Inc. Data Sheet ...
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... Mirror Port -Port 0 can be a RMII mirror port and mirror port 1-11 -Port 12 can be a RMII mirror port and mirror port 0-11, 13-23 -Dedicated MII mirror port can mirror port 0-23 49 Zarlink Semiconductor Inc. Data Sheet PM_DO[1:0] MDS212 PM_DENO Chip 1 4FE 4FE ...
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... Indicate the mirrored port from local or remote device. 0=local 1=remote Whether mirror receiving data or transmitting data 0= Transmission Mirroring, Mirror to Port 0 (Default=0) MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0. I.e., to PM_DO pins. 50 Zarlink Semiconductor Inc. Data Sheet 11 Mirror Port 1=Receiving Mirroring 0 ...
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... A Virtual LAN (VLAN logical, independent workgroup within a network. The members in this workgroup communicate as if they are sharing the same physical LAN segment. VLANs are not limited by the hardware constraints that physically connect traditional LAN segments to a network. As such, VLANs can define a network into multiple logical configurations. MDS212 51 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN-aware switches, so that a VLAN member can be covered by a wide range of switches in a network. GVRP allows both VLAN-aware workstations and switches to issue and revoke VLAN memberships. VLAN-aware switches register and propagate VLAN membership to all ports belonging to the active topology of the VLAN. MDS212 52 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN status for Port 1 V VLAN is Valid C CPU is a member of this VLAN 1st byte: VLAN Index [3:0], 2nd byte: VLAN Index [7:4] Figure 19 - VLAN ID Table 53 Zarlink Semiconductor Inc. Data Sheet FDB block must start from 0 Programmable Size Programmable Size 32KB 16 64KB (up to the number of supported VLAN) ...
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... VLAN, identified by an internal VLAN Index. This table can be accessed by CPU software through CPUIRCMD and CPUIRDAT registers. The contents of this table are set up and maintained by CPU software during VLAN creation, MDS212 100 Figure 20 - VLAN MAC Table 54 Zarlink Semiconductor Inc. Data Sheet VLAN 256 ID ...
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... Internet Group Management Protocol (IGMP) that support automatic multicast group membership. IGMP is configured to create, update, and/or remove MDS212 VLAN Port Enable [11: Priority 55 Zarlink Semiconductor Inc. Data Sheet Tag Enable [11: Port VLAN ID 0 ...
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... Switch Database Memory. If this is a new IP Multicast group, it sets up an entry in the VLAN Port Mapping Table by itself, Whenever an IP Multicast data packet (destination MAC = 01-00-5e-xx-xx-xx, and destination IP address is within the range of 224.0.1.0 and 239.255.255.255) is received, the Search Engine will use the MCT table to look up the MDS212 56 Zarlink Semiconductor Inc. Data Sheet ...
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... Switch CPU is part of this IP Multicast group Next Handle: Pointer to the next entry in a hashed link list. MDS212 MAC2 MAC1 S D Port number MAC5 IP0 VLAN ID VLAN Index IP3 57 Zarlink Semiconductor Inc. Data Sheet MAC0 T MAC4 Next Handle IP2 Next Handle ...
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... Xpipe. Excess multicast forwarding jobs are stored in an internal FIFO, called the MC forwarding FIFO. If the MC forwarding FIFO is full, incoming multicast frames can no longer be forwarded to the remote device. For these blocked multicast frames, their remote destination ports are discarded. MDS212 58 Zarlink Semiconductor Inc. Data Sheet ...
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... The Trunk Port Mapping Table is 32 entries deep (4 groups * 8 hash entries), and each entry is 5 bits wide (1-bit device ID, 4-bit port ID), as show in Figure 21. MDS212 Port Dev TG provided Search Eng (4bit) (1bit) TG Hash Key (2bits) (3bits Hash Key Figure 21 - Port Mapping Table 59 Zarlink Semiconductor Inc. Data Sheet ...
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... Pick one forwarding port per Trunk Group and turn the corresponding bit to 1. (Each Hash Key may have different forwarding port, the rule to pick forwarding port CPU.) FP Mask AND Forwarding ports Figure 22 - Forwarding Port Mask Table 60 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN Member for INDEX=5 Forwarding ports Turn this port off since port 2 has the same TGID of source port 0 61 Zarlink Semiconductor Inc. Data Sheet Device 1 Remote ...
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... All registers are 32-bit wide. They are classified in the following tables: Tag 1. Device Configuration Registers (DCR) GCR Global Control Register DCR0 Device Status Register DCR1 Signature & Revision & ID Register DCR2 Device Configuration Register MDS212 Description Table 9 - MDS212 Register Map 62 Zarlink Semiconductor Inc. Data Sheet Address W/R 7C0 W/-- 7C0 --/R 7C4 W/R 7C8 W/R ...
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... HMCL0 HISC Micro-Code Loading Port-Low HMCL1 HISC Micro-Code Loading Port-High HPRC HISC Priority Control Register MCS0R Micro Sequence 0 Register MCS1R Micro Sequence 1 Register Table 9 - MDS212 Register Map (continued) MDS212 Description 63 Zarlink Semiconductor Inc. Data Sheet Address W/R 7CC --/R 7DC W/R 7E0 --/R 7E4 --/R 7E8 W/R ...
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... Flow Control Holding Time for 10Mbps port AFCHT100 Flow Control Holding Time for 100Mbps port 9. Access Control Function Group 2 (Chip Level controls) APMR Port Mirroring Register Table 9 - MDS212 Register Map (continued) MDS212 Description 64 Zarlink Semiconductor Inc. Data Sheet Address W/R 6DC W/R 6E0 W/R 6E4 W/-- ...
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... MAC Port Configuration Register ECR2 MAC Port Interrupt Mask Register ECR3 MAC Port Interrupt Status Register ECR4 Status Counter Wrap Signal PVIDR PVID Register Table 9 - MDS212 Register Map (continued) MDS212 Description 65 Zarlink Semiconductor Inc. Data Sheet Address W/R 5C4 W/R 5C8 W/R 5CC W/R 5D0 W/R 5D4 ...
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... Table 10 - Global Control Register Direct Access, Description Initialization: Device is in idle state pending for system software initialization. Device Reset: Device is in RESET state. Execution: Device is under normal operation. Table 11 - Device Status Register 66 Zarlink Semiconductor Inc. Data Sheet Write only SYNC ...
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... Signature 8-bit Device Signature 5-bit Device ID (Read/Write) Direct Access, Write/Read Configuration Default = 00 10=90Mhz 11=80Mhz 1 = active high output Default = 0 Default = 128K x 32-bit 11 = 512K x 32-bit 67 Zarlink Semiconductor Inc. Data Sheet Rev ...
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... Default = Learning Disable 0 = Learning Enable Bit [17] Partial Syn Partial Synchronization enable for MAC Table enable Default=0 0= Fully Synchronization for MCT table 1= Partial Synchronization for MCT table Bit [18] Reserved MDS212 01=mode 1 11=mode 3 01= 9 11= TDB 68 Zarlink Semiconductor Inc. Data Sheet ...
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... IP multicast traffic has a privilege over regular multicast traffic. Default=0 0= disable 1= enable Control Bus Mode (Read only bit) Must be 0 CPU Read/Write Control Polarity Selection (Read only bit R/ W/R# Switching Mode (Read only bit) Default Managed mode 1 = Unmanaged mode 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... Read FIFO Empty, the FIFO that CPU interface reads is empty Write FIFO Empty, the FIFO that CPU writes is empty Reserved Queue Manager Interface Status CPU Input Queue is ready for CPU to write into queue CPU Input Queue is full WCL 70 Zarlink Semiconductor Inc. Data Sheet Que_Stat Mem_Stat ...
Page 71
... CPU encounters empty Free Mail list situation. Interrupt from MAC ports Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12. Search Engine found looped MCT Chain. 71 Zarlink Semiconductor Inc. Data Sheet Identify the sources of interrupt with Direct Access,Read only Defines the interrupt sources to be ...
Page 72
... Buffer memory address Bit [20:2] – (Bit [1:0] = 00) Indicates the Address is Internal or External memory I/E=0 Internal memory I/E=1 External memory Must be 00001 Byte lane enables Bit [31] Bit [30] BE [3] BE [2] BE [0] BE [1] 72 Zarlink Semiconductor Inc. Data Sheet Bit [29] Bit [28] BE [1] BE [0] BE [2] BE [3] ...
Page 73
... FIFO, Write I/E Address MA[20:2] Lock Flag LK=0 Unlock Swap Byte Order Buffer memory address Bit [20:2] – (Bit [1:0] = 00) Indicate the Address is Internal or External memory I/E=0 Internal memory 73 Zarlink Semiconductor Inc. Data Sheet LK=1 Lock I/E=1 External memory ...
Page 74
... Direct Access, Read only Byte[ Byte[2] Direct Access VMACB VLMS Default=11 10=32K (for 128 VLANs) 11=64K (for 256 VLANs) 74 Zarlink Semiconductor Inc. Data Sheet ……01000 = 8 D-word 10000 = 16 D-word 0 Byte[0] 0 Byte[3] Write/Read 5 0 VLAN ID BASE ...
Page 75
... CPU can set four level watermarks, which are programmable. 00=25% 01=50% Direct Access ST_ADR Read/Write burst (length) of RAM Block. (Unit = 1double words) Read/Write Start Address. RAM Block Access Write/Read indicator 1 = Write 75 Zarlink Semiconductor Inc. Data Sheet Write/Read MAX_MC_FD 10=75% 11=100% Write/Read 0 BST_CNT 0 = Read END_ADR cannot ...
Page 76
... Aging Time = (Number of valid FCB Buffers* Aging Timer Base) msec Direct Access Buffer Low Threshold – The number of frame control buffer handles left in the Queue to be considered as running low and trigger the interrupt to the CPU. 76 Zarlink Semiconductor Inc. Data Sheet 0 Write/Read 0 Write/Read Write/Read ...
Page 77
... Selection for Low or High Limit of Buffer Counter for Remote device 13 bits maps to 13 ports in Remote Device 1 = select hi limit Direct Access, 32-bit data from CPU input queue Direct Access, CPU Output Queue Entry 77 Zarlink Semiconductor Inc. Data Sheet Write/Read 0 Low Limit Write/Read 0 Lp_Hi_Low Sel ...
Page 78
... Start State: Reset IP=0, and start HISC execution. Execution State: Continue HISC execution without reset IP. Illegal State Direct Access, 19 HISC Instruction Word [31:0] HISC Instruction Word has total 40 bit-wide. Needs to be broken into two registers. 78 Zarlink Semiconductor Inc. Data Sheet Write/Read ...
Page 79
... Direct Access DataBit[31:0] Data Bit [31:0] to the sequencer RAM (The length of Micro Sequence Data is 54-bit, Need to be broken into tow registers) Direct Access (Write only bits) 79 Zarlink Semiconductor Inc. Data Sheet Write/Read 0 HISC Instruction [39:32] Write/Read Write/Read ...
Page 80
... Unicast to CPU Rate Restricts the number of frames within the Time window defined in bit[15:12] Direct Access, Write/Read MCT Aging Timer Direct Access, Write/Read 8 7 8-bit Table entry Index Value set Zarlink Semiconductor Inc. Data Sheet 0 Multicast to CPU Rate 0 0 Entry Index ...
Page 81
... Multicast timer Unicast timer Unit time = 80 nsec.(for 64Bytes Frame.) Direct Access MCT threshold Alert system when free MCT entries are below this threshold Direct Access, 0=Ready 81 Zarlink Semiconductor Inc. Data Sheet Write/Read Port ID Write/Read 3 0 ...
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... Direct Access, 20 Entry Handle Entry handle, the bit [2:0] always 2’b000 Link List is Empty. (Read only) Link List is Ready. (Same as bit [1] of LKS register) (Read only) Direct Access VLAN Type Code 82 Zarlink Semiconductor Inc. Data Sheet Write/Read Write/Read ...
Page 83
... Transmission FIFO Threshold in Bytes (Default =0) Unit=8Bytes 0= Cut Through at the destination 100M port When the value does not equal zero, it indicates the port cannot start sending frames out, until the TxFIFO reaches the threshold or EOF. 83 Zarlink Semiconductor Inc. Data Sheet QSW0 ...
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... Data field contains valid data from the PHYs. Data field contains invalid data from the PHYs. Data field is not ready to be read by Switch Manager CPU. Table 13 - AMIIS - MII Status Register 84 Zarlink Semiconductor Inc. Data Sheet Write only DATA (16-bit) Read only ...
Page 85
... Direct Access Content of Input Flow Control Frame[63:32] Direct Access XON_Thd Defines the minimum # of free Frame Buffers before transmitting XON flow control frame. 85 Zarlink Semiconductor Inc. Data Sheet address Write only 8 7 Write only 8 7 Write/Read ...
Page 86
... Direct Access MAC 2 MAC 1 MAC MAC Address Byte [3:0] h600 MAC Address Byte [5:4] h604 Direct Access MAC 1 MAC5 86 Zarlink Semiconductor Inc. Data Sheet » offreeFCB ¼ » 8 Write/Read 8 7 MAC 0 MAC Frame Type Write/Read 0 MAC 0 MAC 4 0 ...
Page 87
... MAC Offset address for Port 10 Bit [15:12] MAC Offset address for Port 11 Bit [31:16] Reserved MDS212 Direct Access Port4_offset Port3_offset Port2_offset Direct Access Port11_offset 87 Zarlink Semiconductor Inc. Data Sheet Write/Read Port1_offset Port0_offset Write/Read Port10_offset Port9_offset Port8_offset 0 ...
Page 88
... Holding time to remote station for head of line blocking control for 10M port. Direct Access, Write/Read 16 15 HBK_TM_100 Holding time to remote station for head of line blocking control for 100M port. Direct Access Write/Read 16 15 FL_OFF_10m Off time to remote station for 10M Port. 88 Zarlink Semiconductor Inc. Data Sheet ...
Page 89
... Indicates the mirrored port is from a local or remote device. 0=local 1=remote Indicates whether the mirror is receiving data or transmitting data Mirror to Port 0 Default=0) MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0 Direct Access, Write/Read Zarlink Semiconductor Inc. Data Sheet 0 0 Mirror Port ...
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... Trunking Forwarding Port Mask for hash key 4 Trunking Forwarding Port Mask for hash key 5 Trunking Forwarding Port Mask for hash key 6 Trunking Forwarding Port Mask for hash key 7 Direct Access Port trunk mask for trunking hash key 90 Zarlink Semiconductor Inc. Data Sheet Write/Read 0 TK_MSK ...
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... CPU checks CFCBHDL[31],H_RDY ready or not. If so, CPU gets the FCB Handle from CFCBHDL[9:0] MDS212 IP Multicast MAC Address Byte [3:0] IP Multicast MAC Address Byte [5:4] Direct Access, Write/Read 16 15 MAC 2 MAC 1 MAC 5 Direct Access, Write/Read 16 15 MASK 2 MASK 1 MASK 5 91 Zarlink Semiconductor Inc. Data Sheet MAC 0 MAC MASK 0 MASK 4 ...
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... Data Read Ready QCNT FCB BMCT VMAP The index of specified entry Entry index[3:0] Entry index[7:0] Entry index[9:0] Entry index[9:0] Entry index[5:0] Write or Read the table entry 0=Read 1=Write 92 Zarlink Semiconductor Inc. Data Sheet 0 FCB_Handle [11: MCID W/R Entry Index [9:0] 0 ...
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... Data[95:64 multicast ID FIFO data output (Note that for this version VLAN Tag Enable [12:0] Identify the ports associated with each VLAN 0 = disable 1 = enable 0 = disable 1 = enable 93 Zarlink Semiconductor Inc. Data Sheet Write/Read MCID[5: VLAN Port Enable [12:0] 0 ...
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... BM stores free FCB handles. (FCB handle=0 cannot be used FCB_DATA[31:0] FCB_DATA[55:32] Frame Control Block. Refer to Section 9.0 “The High Density Instruction Set Computer (HISC)” on page 37 for detailed data structure ECnt[10:0] Base[11:0] CV RdPt[9:0] 94 Zarlink Semiconductor Inc. Data Sheet BM[11: QS[2:0] WrPt[9:6] Cache Queue Entry[31:17 ...
Page 95
... LED Clock frequency (Default=00) 00=100M/8=12.5Mhz 10=100M/32=3.125Mhz11=100M/64=1.5625Mhz Start Shift out the status bits out from the master device. This bit has no effect on slave chip. Direct Access, x: port n (n=0 - 11) 95 Zarlink Semiconductor Inc. Data Sheet Write/Read 1 0 RDY Write/Read 8 7 UDEF2 ...
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... Trunk Enable 0= Trunk disable 1= Trunk Enable Instructs the Rx MAC to discard incoming Unicast Frames. This feature is used by Spanning Tree. 0X Blocking, all frames (Default state) 10 Learning but not forwarding 11 Forwarding all frames Ingress Filter Enable 96 Zarlink Semiconductor Inc. Data Sheet Write/Read ...
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... Enables MAC Transmitter for transmission Default =0 – Disable Inter-frame Gap (Default=7’d24) Use to adjust the inter-frame gap. (Unit =transmit Clock.) The default is 7'd24, stands for 24 transmit clock (each clock transmit 4 bits). Direct Access, Write/Read x: port number ECR2_p0 ECR2_p1 ECR2_p2 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... Status Wrapped around signal. This bit is set when the MAC determines that the status of physical link has been changed 0=Link Down, 1=Link UP This bit is reset whenever the PHY has identified the lost of physical link integrity. 98 Zarlink Semiconductor Inc. Data Sheet ...
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... Frames with length between 1024-1528 bytes B[21]. C-l Undersize Frames B[22]. C-u Fragment B[23]. D-l CRC B[24]. D-u Short Event B[25]. E-l Collision B[26]. E-u Drop MDS212 Direct Access, Read only x: port number ECR4_p0 ECR4_p1 ECR4_p2 ECR4_p3 ECR4_p4 ECR4_p5 ECR4_p6 ECR4_p7 ECR4_p8 ECR4_p9 ECR4_p10 ECR4_p11 Status Wrapped Signal 99 Zarlink Semiconductor Inc. Data Sheet 0 ...
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... Direct Access, Write/Read x: port number PVIDR_p0 PVIDR _p1 PVIDR _p2 PVIDR _p3 PVIDR _p4 PVIDR _p5 PVIDR _p6 PVIDR _p7 PVIDR _p8 PVIDR _p9 PVIDR _p10 PVIDR _p11 Priority 100 Zarlink Semiconductor Inc. Data Sheet 7 0 Port VLAN ID ...
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... Thermal resistance between junction and case jc When external heat sink is attached, T Note 1: MDS212 +3 +3.6 V +2. +2. (VCC + 3 +70 C AMBIENT Min 2.4 2.0 is reduced by about 8-12% in still air. JA 101 Zarlink Semiconductor Inc. Data Sheet Type Max Unit 100 MHz 220 286 mA 720 936 V 0.4 V VCC + 2.0 V ...
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... X_FCI S_CLK X15 X16 X_DCLKI -100MHZ Parameter Min (ns 102 Zarlink Semiconductor Inc. Data Sheet X17 X18 X19 X20 X21 X22 X23 X24 Note Max (ns 30pf 30pf 30pf 30pf Reference S-CLK Reference S-CLK ...
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... CPU BUS Interface Figure 25 - CPU Bus Interface - Output Valid Delay Timing MDS212 P_CLK P19-max P19-min P_D[31:0] P23-max P23-min P_RDY# P24-max P24-min P_INT P20-max P20-min P_A[10:1] P21-max P21-min P_RWC# P22-max P22-min P_ADS# P25-max P25-min P_GNTC P26-max P26-min P_GNT1 103 Zarlink Semiconductor Inc. Data Sheet ...
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... P10 P_A[10:1] input hold time P11 P_D[31:0] input setup time P12 P_D[31:0] input hold time P15 P_REQC input setup time P16 P_REQC input hold time Table Characteristics - CPU Bus Interface Zarlink Semiconductor Inc. MDS212 P10 P11 ...
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... Figure 27 - Local Memory Interface - Input Setup and Hold Timing MDS212 Parameter Min (ns L_CLK L1 L2 L_D[63:0] 105 Zarlink Semiconductor Inc. Data Sheet -66MHZ Note Max (ns 65pf 50pf 50pf 50pf 50pf 30pf 9 CL =20pF ...
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... L3 max L3 min L4 max L4 min L6 max L6 min L7 max L7 min L8 max L8 min L9 max L9 min -100MHz Min (ns) Max (ns 106 Zarlink Semiconductor Inc. Data Sheet Notes C =50pf =30pf L C =50pf =50pf L C =30pf L C =30pf L C =30pf L ...
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... Figure 30 - Port Mirroring Interface - Output Delay Timing M_CLKI M[11:0]_RXD[1:0] M[11:0]_CRS_DV Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing M_CLKI M[11:0]_TXEN M[11:0]_TXD[1:0] Figure 32 - Reduce Media Independent Interface - Output Delay Timing Zarlink Semiconductor Inc. MDS212 PM1 PM2 PM3 PM4 PM5 PM6-max PM6-min ...
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... Table Characteristics - Reduced Media Independent Interfac MDS212 LE1 LE2-max LE2-min LE3-max LE3-min -50Mz Min (ns) Max (ns) 1 -50Mz Min (ns) Max (ns) 1 108 Zarlink Semiconductor Inc. Data Sheet Notes Reference Input Clock Notes Reference Input Clock ...
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... Parameter LE1 LE_DI Input LE_CLKO Times LE2 LE_DO Output Valid Delay LE3 LE_SYNCO Output Valid Delay Table Characteristics - LED Interface MDS212 Variable Freq. Min (ns) Max (ns 109 Zarlink Semiconductor Inc. Data Sheet Notes Reference Output Clock ...
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... DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0. Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. E1 ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...