CXD2500BQ Sony, CXD2500BQ Datasheet

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... CD Digital Signal Processor Description The CXD2500BQ is a digital signal processing LSI designed for use in compact disc players. It has the following functions: • Wide-frame jitter margin (±28 frames) realized by a built-in 32K RAM. • Bit clock generated by digital PLL for strobing EFM signals. Capture range of ± ...

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... O Topr –20 to +75 Tstg –40 to +125 –AV –0 –AV –0 5.25 3 (5.0 V typ.) DD Topr – –0 0 value is 3.6 V (min.). DD —2— CXD2500BQ °C ° ° the normal-speed playback 2 value is 5.5 V (max.). DD ...

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... Noise over samplling 10 shaper TEST filter 32K RAM EFM Address generator 8 data processor Error corrector CLV processor Timing Generator —3— CXD2500BQ Priority encoder PSSL 49 D/A DAO ...

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... CNIN 77 DATO 78 XLTO 79 CLKO 80 MIRR D2500B —4— CXD2500BQ DA10 DA11 DA12 DA13 ...

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... Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0. Outputs DA12 when PSSL= clock from the 64-bit slot when PSSL=0. Outputs DA11 when PSSL=1, or GTOP when PSSL=0. Outputs DA10 when PSSL=1, or XUGF when PSSL=0. —5— CXD2500BQ =8.6436 MHz LOCK =16.9344 MHz. center ...

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... Inputs SENSE from SSP. Inputs track jump count signal. Outputs serial data to SSP. Latches serial data output to SSP at falling edge. Outputs serial data transfer clock to SSP. Inputs mirror signal to be used by auto sequencer when jumping 16 or more tracks. —6— CXD2500BQ ...

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... The GFS signal turns “H” upon coincidence between Frame Sync and the timing of interpolation protection. • RFCK is a signal generated at 136-µs periods using a crystal oscillator. • C2PO is a signal to indicate data error. • XRAOF is a signal issued when a jitter margin of ±28F is exceeded by the 32K RAM. —7— CXD2500BQ ...

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... V –0 =–0. –0 = —8— CXD2500BQ = Topr=–20 to +75° Max. Unit Related pins ...

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... V V –1.0 IHX DD V ILX WHX WLX t F (Topr=–20 to +75 °C, V Symbol Min. V 2.0 1 —9— CXD2500BQ =AV =5.0 V± Typ. Max. Unit 34 MHz =AV =5.0 V± Typ. Max. Unit 500 500 ns 1,000 V 0 IHX V 0 ...

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... 300 WT 1 WCK WCK 1 Data Address —10— CXD2500BQ = Topr=–20 to +75 ° Typ. Max. Unit 0.65 MHz ns 1 MHz 750ns or more Valid 300ns max ...

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... D3 D2 0. 5.8 ms Data —13— CXD2500BQ AS1 AS0 RXF 1 RXF 0 RXF 1 RXF RXF=0 FORWARD RXF=1 REVERSE D1 D0 0.045 ms 0.022 ms 0.09 ms 0.045 2.9 ms 1.45 ms Data 3 Data 4 ...

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... Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, the channel clock frequency is 4.3218 MHz. Data DSPB A. SEQ D. PLL ON-OFF ON-OFF ON-OFF —14— CXD2500BQ D1 AS0 D. OUT WSEL Mute-F Processing MD2=0 – dB 0dB Application Data BiliGL ...

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... PWM, MD=0 Carrier frequency=132 kHz is set to 0, and 140Hz when T B Processing ASEQ SEIN ( SEIN (SSTOP GFS COMP COUT OV64 Z —15— CXD2500BQ = set ASEQ=1 SEIN (FZC) SEIN (A, S) XBUSY FOK SEIN (Z) GFS COMP COUT OV64 0 ...

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... BiliGL SUB=1 SUB Definition of Bilingual MAIN, SUB, and STEREO MAIN; The input L-ch signal is output to both L-ch and R-ch. Sub: The input R-ch signal is output to both L-ch and R-ch. STEREO: The input L-ch and R-ch signals are output to both L-ch and R-ch respectively. Meaning Meaning BiliGL MAIN=1 MAIN Mute —16— CXD2500BQ ...

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... Data Vari Mute ATT DWN +0.2% +0.1% +0% Meaning Meaning PCM Gain Mute 0 dB —17— CXD2500BQ Data PCT1 PCT2 -0.1% -0.2% XTal 0% Command bit Meaning ATT=0 Attenuation is off. ATT=1 –12dB ECC correction capacity C1: Double, C2: Quadruple C1: Double, C2: Quadruple C1: Double, C2: Double C1: Double, C2: Double ...

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... If Gain CLVS=0, then GCLVS=–12 dB. –6dB If Gain CLVS=1, then GCLVS=0 dB 0dB 0dB +6dB Gain Gain MDS1 MDS0 —18— CXD2500BQ Explanation Only DCLV=1 is effective. DCLV=1 and DCLV=0 are both effective. GMDS –6dB 0dB +6dB ...

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... Automatic switching mode for CLVS and CLVS. This mode is used during normal play status Description (See Timing Chart 1-6.) Description CM2 CM1 CM0 CM0 Mode 0 STOP See Timing Chart 1-7. 0 KICK See Timing Chart 1-8. 0 BRAKE See Timing Chart 1-9. 0 CLVS 0 CLVH 1 CLVP 0 CLVA —19— CXD2500BQ CLVS Gain See “$CX Command.” Explanation ...

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... MON DCLV=1 DCLV PWM MD=0 MDS MDP DCLV=1 DCLV PWM MD=1 MDS MDP FSW and MON are the same as for DCLV=0 Z n·236 (nsec) n Acceleration n·236 (nsec) n=0~31 Output Waveforms with DCLV=1 STOP STOP Z Z STOP L —23— CXD2500BQ Z Deceleration Deceleration ...

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... MDS MDP FSW MON DCLV=1 DCLV PWM MD=0 MDS MDP FSW and MON are the same as for DCLV=0 DCLV=1 DCLV PWM MD=1 MDS MDP FSW and MON are the same as for DCLV=0 KICK KICK KICK —24— CXD2500BQ 7.6µs ...

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... Timing Chart 1-9 DCLV=0 MDS MDP FSW MON DCLV=1 DCLV PWM MD=0 MDS MDP FSW and MON are the same as for DCLV=0 DCLV=1 DCLV PWM MD=1 MDS MDP FSW and MON are the same as for DCLV=0 BRAKE BRAKE —25— CXD2500BQ ...

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... As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is stored. These operations are shown in Time chart 2-3. Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns and 120 µs for both “High” and “Low”. —26— CXD2500BQ ...

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... Timing Chart 2-1 Internal PLL c lock 4.3218± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO S0· Same Subcode Read Timing 750ns max S0·S1 Q S0· Same —27— CXD2500BQ ...

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... SUBQ —28— CXD2500BQ ...

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... The digital PLL features a secondary loop controlled through the primary loop (phase) secondary loop (frequency). When FLFC=1, the secondary loop can be turned off. • When high frequency components such as 3T, 4T, are deviated, turning off the secondary loop will provide better play ability. • However, the capture range will be 50 kHz. —30— CXD2500BQ ...

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... Block Diagram 3-1 OSC 16,9344MHz X'Tal (384Fs) XTSL 2/1 MUX Vari-pitch Digital PLL 1/1000 1/4 1/4 1/1000+n Up down counter n=-217 to 168 Microcomputer control Vari-pitch I/M I/N VCO RFPLL D2500B —31— CXD2500BQ LPF VPCO VCO 19 13.26MHz VCKI PCO FILI FILO CLTV ...

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... C2: 1 error corrected. 0 C2: 2 errors corrected. 1 C2: 3 errors corrected. 0 C2: 4 errors corrected C2: Uncorrectable error. 1 C2: Uncorrectable error. —32— CXD2500BQ C1 pointer reset. C1 pointer set. — — C1 pointer set. C1 pointer set. C1 pointer set. C1 pointer set. C2 pointer reset. C2 pointer reset. C2 pointer reset. C2 pointer reset. ...

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... This is an LSB-first interface made up of LRCK signals with 64-bit clock cycles per LRCK cycle. While the LRCK signal is Low, the data going through this interface is of the left channel. C2 correction Strobe Valid Invalid —33— CXD2500BQ Strobe Valid ...

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... Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous data to SSP is prevented when XBUSY changes from Low to High Table 3-6 Digital Out C bits —36— CXD2500BQ 0 ...

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... FZC after staying High continuously for a longer period than E. System Configuration for Auto Sequencer Operation (Example) RF MIRR FOK C.out SENS DATA SSP CLK XLT MIRR DATA FOK CLOK XLAT SENS CXD2500B CNIN SEIN DATO CLKO XLTO Figure 3-7 —37— CXD2500BQ Micro-computer ...

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... XLAT FOK SEIN(FZC) BUSY Command to SSP $03 Figure 3-8 (b) Timing chart for auto focus operation Auto focus Checking whether FZC has stayed High longer than time E set in Register 5. FOK=H NO YES FZC=H NO YES FZC=L NO YES Focus servo ON END Blind E —38— CXD2500BQ $08 ...

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... CNIN signals and above, MIRR signals are counted instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a large track move ranging from several thousand to several tens of thousand tracks actual use, however subject to limitation imposed by the —39— CXD2500BQ 16 . The ...

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... Figure 3-9 (b) Timing chart for 1-track jump 1 Track Track Kick (REV kick is made for REV jump.) Sled servo WAIT (Blind A) CNIN= NO YES Track REV (FWD kick is made for REV jump.) Kick WAIT (Brake B) Track sled Servo ON END Brake B $2C ($28) —40— CXD2500BQ $25 ...

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... Track, Sled FWD Kick WAIT (Blind A) (5 CNINs are counted.) CNIN YES Track, REV Checking whether the CNIN period has FWD Kick exceeded the value of overflow C. C=Overflow? NO YES Track, Sled Servo ON END CNIN 5count $2E ($2B) —41— CXD2500BQ Overflow C $25 ...

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... Figure 3-11 (b) Timing chart for 2N track jump 2N Track Track, Sled FWD Kick WAIT (Blind A) For the first 16 times CNIN is counted. After that MIRR is counted. NO YES Track, REV Kick C=Overflow NO YES Track Servo ON WAIT (Klick D) Sled Servo ON END CNIN (MIRR) N count $2E ($2B) —42— CXD2500BQ Kick D Overflow $26 ($27) $25 ...

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... Figure 3-12 (a) Flow chart of M track move $4E (REV=$4F) latch XLAT CNIN (MIRR) BUSY Blind A Commands to SSP $22 ($23) Figure 3-12 (b) Timing chart for M track move WAIT (Blind A) CNIN is counted for M<16, MIRR is counted for M 16. NO YES Track, Sled Servo ON END CNIN (MIRR) M count —43— CXD2500BQ $25 ...

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... CLVS U/D Gain 0, –6dB CLV P/S KICK, BRAKE STOP MDS Error Measure 2/1 MUX Gs(Gain) 1/2 + Mux CLV – P/S Over Sampling Filter-2 Noise Shape Modulation Mode Select DCLVMD Figure 3-14 Block diagram —44— CXD2500BQ MDP Error Measure Over Sampling Filter-1 GP(Gain) CLV P CLV S MDP MDS ...

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... Asymmetry correction Block diagram and circuit example are shown on Fig. 3-15. 28 ASYE BIAS Figure 3-15 Asymmetry correction application circuit example D2500B ASYO ASYI —45— CXD2500BQ ...

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... Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same SLD SPD C12 C13 C14 DD —46— CXD2500BQ ...

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... COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g 80PIN QFP (PLASTIC) 24.0 ± 0.3 + 0.4 20.0 – 0 0.15 0.8 0.35 – 0.1 2.7 ± 0.1 ± 0.12 M 3.1 MAX 22.6 PACKAGE STRUCTURE EPOXY RESIN PACKAGE MATERIAL LEAD TREATMENT SOLDER PLATING QFP-80P-L121 QFP080-P-1420-AX 42 ALLOY LEAD MATERIAL PACKAGE WEIGHT 1.6g —47— CXD2500BQ + 0.1 0.15 – 0.05 0. 0.2 0.1 – 0.05 + 0.2 0.1 – 0.05 0° to 10° 0.15 ...

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... NOTE: Dimension “ ” does not include mold protrusion. SONY CODE EIAJ CODE JEDEC CODE QFP 80PIN (PLASTIC) 23.9 ± 0.2 20.0 ± 0 – 0.8 0.15 M 1.45 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE EPOXY RESIN PACKAGE MATERIAL LEAD TREATMENT SOLDER PLATING QFP-80P-L051 LEAD MATERIAL QFP080-P-1420-AH 42 ALLOY 1.6g PACKAGE WEIGHT —48— CXD2500BQ A ...