LH5268AD-10LL Sharp, LH5268AD-10LL Datasheet

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LH5268AD-10LL

Manufacturer Part Number
LH5268AD-10LL
Description
CMOS 32K x 8 static RAM
Manufacturer
Sharp
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH5268AD-10LL
Manufacturer:
MICRON
Quantity:
311
Part Number:
LH5268AD-10LL
Manufacturer:
SHARP
Quantity:
20 000
LH5268A
FEATURES
8,192
Access time: 100 ns (MAX.)
Power consumption:
Fully-static operation
Three-state outputs
Single +5 V power supply
TTL compatible I/O
Packages:
Operating:
Standby:
Data retention:
28-pin, 600-mil DIP
28-pin, 300-mil SK-DIP
28-pin, 450-mil SOP
220 mW (MAX.)
55 mW (MAX.) (t
220 W (MAX.)
3.0 W (V
8 bit organization
CC
= 3 V, T
RC
, t
WC
A
= 25 C)
= 1 s)
DESCRIPTION
bits. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
The LH5268A is a static RAM organized as 8,192
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
Figure 1. Pin Connections for DIP, SK-DIP,
CMOS 64K (8K
GND
I/O
I/O
I/O
A
NC
A
A
A
A
A
A
A
A
12
and SOP Packages
6
4
3
2
1
2
3
7
5
1
0
10
12
13
14
11
2
3
4
6
7
8
9
5
1
27
18
17
28
26
25
24
23
22
21
20
19
16
15
8) Static RAM
A
I/O
I/O
I/O
I/O
CE
A
A
OE
A
CE
I/O
V
WE
8
9
11
CC
10
7
6
5
4
2
8
1
TOP VIEW
5268A-1
8
1

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LH5268AD-10LL Summary of contents

Page 1

LH5268A FEATURES 8,192 8 bit organization Access time: 100 ns (MAX.) Power consumption: Operating: 220 mW (MAX (MAX Standby: 220 W (MAX.) Data retention: 3 ...

Page 2

LH5268A I I DATA CONTROL 16 I/O 5 I/O ...

Page 3

CMOS 64K (8K 8) Static RAM TRUTH TABLE NOTE ...

Page 4

LH5268A AC CHARACTERISTICS (1) READ CYCLE ( + PARAMETER SYMBOL Read cycle time t RC Address access time Chip enable 1 ACE1 access time ( ACE2 ...

Page 5

CMOS 64K (8K 8) Static RAM 1 CAPACITANCE ( MHz) A PARAMETER SYMBOL Input capacitance C IN Input/output capacitance C I/O NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS ...

Page 6

LH5268A OUT NOTE 'HIGH ACE1 t LZ1 t ACE2 t LZ2 OLZ DATA VALID Figure 4. Read Cycle ...

Page 7

CMOS 64K (8K 8) Static RAM OUT D IN NOTES: 1. The writing occurs during an overlapping period defined as the time from ...

Page 8

LH5268A (NOTE 6) D OUT D IN NOTES: 1. The writing occurs during an overlapping period defined as the time from the last occuring transition, ...

Page 9

CMOS 64K (8K 8) Static RAM PACKAGE DIAGRAMS 28DIP (DIP028-P-0600 36.30 [1.429] 35.70 [1.406] 2.54 [0.100] 0.60 [0.024] TYP. 0.40 [0.016] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28DIP (DIP028-P-0300 35.00 [1.378] 34.40 [1.354] 2.54 ...

Page 10

... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH5268A X Device Type Package Example: LH5268AD-10LL (CMOS 64K ( Static RAM, Low-Low-power standby, 100 ns, 28-pin, 300-mil DIP)) 10 1.70 [0.067] 15 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457] 14 1.70 [0.067] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2 ...

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