LH52258AD-25 Sharp, LH52258AD-25 Datasheet
LH52258AD-25
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LH52258AD-25 Summary of contents
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LH52258A FEATURES Fast Access Times: 20/25 ns Low-Power Standby when Deselected TTL Compatible I 10% Supply Fully-Static Operation JEDEC Standard Pinout Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION The LH52258A is a high-speed 262,144 bit static ...
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LH52258A TRUTH TABLE MODE Not Selected High Selected High Read Data Out Write Data ...
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CMOS 32K 8 Static RAM ABSOLUTE MAXIMUM RATINGS PARAMETER Potential CC SS Input Voltage Range 2 DC Output Current Storage Temperature Range Power Dissipation (Package Limit) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ ...
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LH52258A AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Output Load, Timing Tests 1,2 CAPACITANCE PARAMETER C (Input Capacitance (I/O Capacitance) DQ NOTES: 1. Capacitances are maximum values ...
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CMOS 32K 8 Static RAM AC ELECTRICAL CHARACTERISTICS SYMBOL t Read Cycle Time RC t Address Access Time AA t Output Hold from Address Change Low to Valid Data Low to Output Active ELZ ...
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LH52258A TIMING DIAGRAMS – READ CYCLE Read Cycle No. 1 Chip is in Read Mode HIGH LOW and G is LOW. Read cycle timing is referenced from when all addresses are stable until the first address ...
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CMOS 32K 8 Static RAM TIMING DIAGRAMS – WRITE CYCLE Addresses must be stable during Write cycles. The outputs will remain in the High-Z state LOW when E goes LOW HIGH, the outputs will ...
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LH52258A PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300 35.00 [1.378] 34.40 [1.354] 2.54 [0.100] 0.56 [0.022] TYP. 0.36 [0.014] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28SOJ (SOJ28-P-300 18.7 [0.736] 18.3 [0.720] 0.53 [0.021] 0.33 [0.013] 1.27 [0.050] ...
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CMOS 32K 8 Static RAM ORDERING INFORMATION LH52258A Device Type Package Example: LH52258AK-25 (CMOS 32K x 8 Static RAM, 25 ns, 28-pin, 300-mil SOJ Speed 20 Access Time (ns 28-pin, 300-mil DIP (DIP28-P-300) K 28-pin, ...