MX28F1000PPC-12C4 Macronix International Co., MX28F1000PPC-12C4 Datasheet

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MX28F1000PPC-12C4

Manufacturer Part Number
MX28F1000PPC-12C4
Description
Manufacturer
Macronix International Co.
Datasheet

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FEATURES
• 131,072 bytes by 8-bit organization
• Fast access time: 70ns(Vcc:5V±5%; CL:35pF)
• Low power consumption
• Programming and erasing voltage 12V ± 5%
• Command register architecture
• Optimized high density blocked architecture
GENERAL DESCRIPTION
The MX28F1000P is a 1-mega bit Flash memory or-
ganized as 128K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F1000P is packaged in 32-pin PDIP, PLCC
and TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
The standard MX28F1000P offers access times as
fast as 70 ns, allowing operation of high-speed
microprocessors without wait states.
bus contention, the MX28F1000P has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX28F1000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout.
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
P/N: PM0340
– 50mA maximum active current
– 100uA maximum standby current
– Byte Programming (15us typical)
– Auto chip erase 5 seconds typical
– Block Erase
– Four 4-KB blocks
(including preprogramming time)
90/120ns(Vcc:5V±10%; CL:100pF)
To eliminate
The
The
1
1M-BIT [128K x 8] CMOS FLASH MEMORY
• Auto Erase (chip & block) and Auto Program
• 10,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Advanced CMOS Flash memory technology
• Compatible with JEDEC-standard byte-wide 32-pin
• Package type:
MX28F1000P
perform the Auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
– Seven 16-KB blocks
– DATA polling
– Toggle bit
EPROM pinouts
– 32-pin plastic DIP
– 32-pin PLCC
– 32-pin TSOP (Type 1)
MX28F1000P
uses a 12.0V ± 5% VPP supply to
REV. 1.6,JAN. 19, 1999

Related parts for MX28F1000PPC-12C4

MX28F1000PPC-12C4 Summary of contents

Page 1

FEATURES • 131,072 bytes by 8-bit organization • Fast access time: 70ns(Vcc:5V±5%; CL:35pF) 90/120ns(Vcc:5V±10%; CL:100pF) • Low power consumption – 50mA maximum active current – 100uA maximum standby current • Programming and erasing voltage 12V ± 5% • Command register ...

Page 2

MX28F1000P Block Address and Block Structure A16 A15 A14 A13 ...

Page 3

PIN CONFIGURATIONS 32 PDIP VCC VPP A16 2 31 A15 A12 29 A14 A13 A11 ...

Page 4

BLOCK DIAGRAM CE CONTROL OE INPUT WE LOGIC ADDRESS LATCH A0-A16 AND BUFFER Q0-Q7 P/N: PM0340 MX28F1000P PROGRAM/ERASE HIGH VOLTAGE MX28F1000P FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 MODE ...

Page 5

AUTOMATIC PROGRAMMING The MX28F1000P is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical room temperature chip programming time of the MX28F1000P is ...

Page 6

TABLE 1. COMMAND DEFINITIONS COMMAND BUS CYCLES Read Memory 1 Read Identified codes 2 Setup auto erase/ 2 auto erase (chip) Setup auto erase/ 2 auto erase (block) Setup auto program/ 2 program Setup Erase/ 2 Erase (chip) Setup Erase/ ...

Page 7

COMMAND DEFINITIONS When low voltage is applied to the VPP pin, the con- tents of the command register default to 00H, enabling read-only operation. Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing ...

Page 8

READ COMMAND While VPP is high, for erase and programming, mem- ory contents can also be accessed via the read com- mand. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. ...

Page 9

The Automatic set-up block erase command is a com- mand only operation that stages the device for auto- matic electrical erasure of selected ...

Page 10

The MX28F1000P applies an internally generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each ...

Page 11

ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & VPP o CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance ...

Page 12

AC CHARACTERISTICS SYMBOL PARAMETER tACC Address to Output Delay tCE CE to Output Delay tOE OE to Output Delay tDF OE High to Output Float tOH Address to Output hold TEST CONDITIONS: • Input pulse levels: 0.45V/2.4V • Input rise ...

Page 13

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS SYMBOL PARAMETER ILI Input Leakage Current ILO Output Leakage Current ISB1 Standby VCC current ISB2 ICC1 (Read) Operating VCC Current ICC2 ICC3 (Program) ICC4 (Erase) ICC5 (Program Verify) ICC6 (Erase Verify) IPP1 (Read) VPP ...

Page 14

AC CHARACTERISTICS TA = -40 SYMBOL PARAMETER tVPS VPP setup time tOES OE setup time tCWC Command programming cycle tCEP WE programming pulse width tCEPH1 WE programming pluse width High tCEPH2 WE programming pluse width High tAS Address setup time ...

Page 15

SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL = 100 pF including jig capacitance(35pF for 70 ns parts) SWITCHING TEST WAVEFORMS 2 TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic ...

Page 16

AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are excuted auto- matically by internal control circuit. completion can be verified by DATA polling ...

Page 17

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART P/N: PM0340 START Apply VppH Write Set up auto program Command (40H) Write Auto program Command(A/D) NO Toggle Bit Checking DQ6 not Toggled YES NO Verify Byte Ok YES NO Last Byte YES Auto Program Completed ...

Page 18

AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verify is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic ...

Page 19

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N: PM0340 START Apply VppH Write Set up auto chip Erase Command (30H) Write Auto chip Erase Command(30H) Toggle Bit Checking No DQ6 not Toggled YES DATA Polling No DQ7 = 1 YES Auto Chip ...

Page 20

AUTOMATIC BLOCK ERASE TIMING WAVEFORM Block data indicated by A12 to A16 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle ...

Page 21

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART P/N: PM0340 START Apply VppH Write Set up auto block Erase Command (20H) Write Auto block Erase Command(D0H) to Load Block Address Load Block Address Last Block NO to Erase YES Wait 200us Toggle Bit ...

Page 22

COMPATIBLE CHIP ERASE TIMING WAVEFORM All data in chip are erased. Control verification and additional erasure externally according tocompatible chip erase flowchart. Vcc 5V 12V Vpp 0V tVPS A0 ~ A16 WE CE tOES OE Q7 Q0~Q6 Command #20H Command ...

Page 23

COMPATIBLE BLOCK ERASE This device can be applied to the compatible block erase algorithm shown in the following flowchart. This algorithm allows to obtain faster erase time by the block (16K byte COMPATIBLE BLOCK ERASE FLOWCHART BLOCK ERASE FLOW P/N: ...

Page 24

ERASE VERIFY FLOW INCREMENT ADDRESS P/N: PM0340 MX28F1000P START APPLY VPP = VPPH ADDRESS = FIRST ADDRESS OF ERASED BLOCKS OR LAST VERIFY FAILED ADDRESS WRITE ERASE VERIFY COMMAND ( A0H ) WAIT ERSVFY FFH ? YES ...

Page 25

COMPATIBLE BLOCK ERASE TIMING WAVEFORM Indicated block data (16 Kbyte) are erased. Control verification and additional erasure externally according to compatible block erase flowchart. Setup block erase/erase command Vcc 5V 12V Vpp 0V tVPS A0 ~ A13 Block A14 ~ ...

Page 26

VPP HIGH READ TIMING WAVEFORM Vcc 5V 12V Vpp tVPS A16 WE CE tOES tCEP OE tDS Q0-Q7 Command in VPP LOW ID CODE READ TIMING WAVEFORM VID VIH A9 VIL A10-A16 VIH ...

Page 27

VPP HIGH ID CODE READ TIMING WAVEFORM Vcc 5V 12V Vpp tVPS A16 WE CE tOES OE Q0-Q7 RESET TIMING WAVEFORM Vcc 5V 12V Vpp tVPS A16 WE CE tOES OE Q0-Q7 P/N: ...

Page 28

TOGGLE BIT, DATA POLLING TIMING WAVEFORM Toggle bit appears in Q6, when program/erase is opperating. DATA polling appears in Q7 during pro- gramming or erase. HIGH WE Vpp 12V HIGH-Z DURING P/E HIGH-Z Q7 DATA DURING P ...

Page 29

... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX28F1000PPC-70C4 70 MX28F1000PPC-90C4 90 MX28F1000PPC-12C4 120 MX28F1000PQC-70C4 70 MX28F1000PQC-90C4 90 MX28F1000PQC-12C4 120 MX28F1000PTC-70C4 70 MX28F1000PTC-90C4 90 MX28F1000PTC-12C4 120 MX28F1000PRC-70C4 70 MX28F1000PRC-90C4 90 MX28F1000PRC-12C4 120 MX28F1000PPI-70 70 MX28F1000PPI-90 90 MX28F1000PPI-12 120 MX28F1000PQI-70 70 MX28F1000PQI-90 90 MX28F1000PQI-12 120 MX28F1000PTI-70 70 MX28F1000PTI-90 90 MX28F1000PTI-12 120 MX28F1000PRI-70 70 MX28F1000PRI-90 90 MX28F1000PRI-12 120 P/N: PM0340 MX28F1000P ...

Page 30

PACKAGE INFORMATION 32-PIN PLASTIC DIP ITEM MILLIMETERS INCHES A 42.13 max. 1.660 max. B 1.90 [REF] .075 [REF] C 2.54 [TP] .100 [TP] D .46 [Typ.] .050 [Typ.] E 38.07 1.500 F 1.27 [Typ.] .050 [Typ.] G 3.30 ± .25 ...

Page 31

PLASTIC TSOP ITEM MILLIMETERS INCHES A 20.0 ± .20 .078 ± .006 B 18.40 ± .10 .724 ± .004 C 8.20 max. .323 max. D 0.15 [Typ.] .006 [Typ.] E .80 [Typ.] .031 [Typ.] F .20 ± .10 .008 ...

Page 32

Note. Revision History Revision # Description 1.4 Fast access time 150ns and 1,000 times erase cycles removed. Tsop pin configuration diagram rotated 180°. The flow chart of block erase corrected. 1.5 Fast access time 70ns added. 1.6 1)Absolute max. ratings:TA=-40°C ...

Page 33

... TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 33 MX28F1000P ...

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