MX26L6419TC-10 Macronix International Co., MX26L6419TC-10 Datasheet

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MX26L6419TC-10

Manufacturer Part Number
MX26L6419TC-10
Description
Manufacturer
Macronix International Co.
Datasheet
FEATURES
• 3.0V to 3.6V operation voltage
• Block Structure
• Fast random / page mode access time
• 128-bit Protection Register
• 16-Word Write Buffer
• Enhanced Data Protection Features Absolute Protec-
Performance
• Low power dissipation
• High Performance
• Program/Erase Endurance cycles: 100 cycles
GENERAL DESCRIPTION
The MXIC's MX26L6419 series MTP use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell. The device provide the high den-
sity MTP memory solution with reliable performance and
most cost-effective.
The device organized as by 16 bits of output bus. The
device is packaged in 48-Lead TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
P/N:PM0946
- 64 x 64Kword Erase Blocks
- 100/25 ns Read Access Time (page depth:8-word)
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
- 14 us/word Effective Programming Time
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
- Block erase time: 2s typ.
- Word programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
64M [x16] SINGLE 3V PAGE MODE MTP MEMORY
1
Software Feature
• Support Common Flash Interface (CFI)
Hardware Feature
• ACC pin
• VPEN pin
• VCCQ Pin
• RESET pin
Packaging
Technology
electrical erasure and programming. The device uses a
command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
- MTP device parameters stored on the device and
provide the host system to access.
- 12V VPP for fast program/erase mode.
- For Erase /Program/ Block Lock enable.
- The output buffer power supply, control the device 's
output voltage.
- Hardware reset
- 48-Lead TSOP
- Two bits per cell Nbit (0.25u) MTP Technology
ADVANCED INFORMATION
MX26L6419
REV. 0.3, OCT. 08, 2003

Related parts for MX26L6419TC-10

MX26L6419TC-10 Summary of contents

Page 1

FEATURES • 3.0V to 3.6V operation voltage • Block Structure - 64 x 64Kword Erase Blocks • Fast random / page mode access time - 100/25 ns Read Access Time (page depth:8-word) • 128-bit Protection Register - 64-bit Unique Device ...

Page 2

PIN CONFIGURATION 48-TSOP (12mm x 20mm) A15 1 A14 2 A13 3 A12 4 A11 5 A10 A21 9 A20 RESET 12 ACC 13 VPEN 14 A19 15 A18 16 A17 17 ...

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BLOCK DIAGRAM CE CONTROL OE INPUT WE LOGIC RESET ADDRESS LATCH A0-A21 AND BUFFER Q0-Q15 P/N:PM0946 MX26L6419 PROGRAM/ERASE HIGH VOLTAGE MTP ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV DATA LATCH PROGRAM DATA LATCH I/O BUFFER 3 ...

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Figure 1. Block Architecture MTP memory reads erases and writes in-system via the local CPU. All bus cycles to or from the MTP memory conform to standard microprocessor bus cycles. 3FFFFF 1FFFFF P/N:PM0946 A21~A0 64-Kword Block 3F0000 . . . ...

Page 5

Table 1. Bus Operations Command Read Output Sequence Array Disable Notes 3,4 RESET VIH VIH CE Enabled Enabled Disabled X OE (1) VIL VIH WE (1) VIH VIH Address X X VPEN (2) Data out High Z ...

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FUNCTION The device includes on-chip program/erase control cir- cuitry. The Write State Machine (WSM) controls block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register in- dicates ...

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COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid register command sequences. When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled. ...

Page 8

NOTES: 1. Bus operations are defined in Table Any valid address within the device Address within the block Identifier Code Address: see Figure 2 and Table 13 Query database Address. ...

Page 9

Figure 2. Device Identifier Code Memory Map 3FFFFF 3F0003 3F0002 3F0000 3EFFFF 1F0003 1F0002 1F0000 1EFFFF 01FFFF 010003 010002 010000 00FFFF 000004 000003 000002 000001 000000 NOTE: Data is always given on the low byte in x16 mode (upper byte ...

Page 10

Read Array Command The device is in Read Array mode on initial device power up and after exit from power down writing FFH to the Command User Interface. The read configuration reg- ister defaults to asynchronous read page ...

Page 11

In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped from ...

Page 12

Query Structure Overview The Query command causes the MTP component to display the Common Flash Interface (CFI) Query structure or "database". The structure sub-sections and address locations are summarized below. Table 5. Query Structure (1) Offset Sub-Section 00h 01h (BA+2)h ...

Page 13

CFI Query Identification String The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 7. CFI Identification Offset Length Description 10h 3 ...

Page 14

Device Geometry Definition This field provides critical details of the MTP device geometry. Table 9. Device Geometry Definition Offset Length Description 27h 1 "n" such that device size = 2 28h 2 MTP device interface: x8 async(28:00,29:00), x16 async(28:01,29:00), x8/x16 ...

Page 15

Primary-Vendor Specific Extended Query Table Certain MTP features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 10. Primary Vendor-Specific Extended Query Offset(1) Length Description P=31h (Optional MTP Features and Commands) (P+0)h ...

Page 16

Table 11. Protection Register Information Offset(1) Length Description P=31h (Optional MTP Features and Commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field ...

Page 17

DEVICE OPERATION SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. This mode is intended for use by programming equipment for the ...

Page 18

Table 14. Status Register Definitions High Z Symbol When Status Busy? SR.7 No WRITE STATE MACHINE STATUS SR.6 Yes RESERVED SR.5 Yes ERASE AND CLEAR LOCK-BITS STATUS SR.4 Yes PROGRAM AND SET LOCK-BIT STATUS SR.3 Yes PROGRAMMING VOLTAGE STATUS SR.2 ...

Page 19

READ STATUS REGISTER COMMAND The Status Register is read after writing the Read Status Register command of 70H to the Command User Inter- face. Also, after starting the internal operation the de- vice is set to the Read Status Register ...

Page 20

The 12V ACC mode enhances programming performance during the short period of time typically found in manu- facturing processes; however not intended for ex- tended use. ACC pin may be connected to 12V for a total of 80 ...

Page 21

Read Configuration The device will support both asynchronous page mode and standard word reads. No configuration is required. Status register and identifier only support standard word single read operations. Table 16. Read Configuration Register Definition 15(A15) 14 ...

Page 22

Set Block Lock-Bit Commands This device provided the block lock-bits, to lock and unlock the individual block. To set the block lock-bit, the two cycle Set Block Lock-Bit command is requested. This command is invalid while the WSM is running. ...

Page 23

The CUI latches commands issued by system software and is not altered by VPEN, CE transitions, or WSM ac- tions. Its state is read array mode upon power-up, after exit from reset/power-down mode, or after VCC transi- tions below VLKO. ...

Page 24

Table 17. Word-Wide Protection Register Addressing Word Use A7 LOCK Both 1 0 Factory 1 1 Factory 1 2 Factory 1 3 Factory 1 4 User 1 5 User 1 6 User 1 7 User 1 NOTE: 1. All address ...

Page 25

Figure 4. Write to Buffer Flowchart Check Ready Status - Read Status Register Command not required - Perform read operation - Read Ready Status on signal D7 Write Buffer Data - Fill write buffer up to word count - Address=Address(es) ...

Page 26

Figure 5. Status Register Flowchart - Set/Reset by WSM - Set by WSM - Reset by user - See Clear Status Register Command P/N:PM0946 Start Command Cycle - Issue Status Register Command - Address = any device address - Data ...

Page 27

Figure 6. Word Programming Flowchart Start Write 40H, Address Write Data and Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3= 0 ...

Page 28

Figure 7. Block Erase Flowchart Write 20H to Block Address Write Confirm D0H to Block Address P/N:PM0946 Start Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Erase MTP Block(s) Completed 28 MX26L6419 REV. 0.3, OCT. 08, ...

Page 29

Figure 8. Set Block Lock-Bit Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0946 Start Write 60H, Block Address Write 01H, Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See ...

Page 30

Figure 9. Clear Lock-Bit Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0946 Start Write 60H Write D0H Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error ...

Page 31

Figure 10. Protection Register Programming Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0946 Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Program Completed Read Status Register Data ...

Page 32

ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...

Page 33

DC Characteristics Symbol Parameter ILI Input and VPEN Load Current ILO Output Leakage Current ICC1 VCC Standby Current ICC2 VCC Power-Down Current ICC3 VCC Page Mode Read Current ICC5 VCC Program or Set Lock-Bit Current ICC6 VCC Block Erase or ...

Page 34

DC Characteristics, Continued Symbol Parameter VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage VPENLK VPEN Lockout during Program, 2,3,4 Erase and Lock-Bit Operations VPENH VPEN during Block Erase, Program, or Lock-Bit Operations ...

Page 35

Figure 11. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V VCCQ Input VCCQ/2 0.0 Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0". Input timing being, and output timing ends, at VCCQ/2V (50% of ...

Page 36

AC Characteristics --Read-Only Operations (1,2) Versions (All units in ns unless otherwise noted) Sym Parameter tAVAV Read/Write Cycle Time tAVQV Address to Output Delay tELQV CEX to Output Delay tGLQV OE to Non-Array Output Delay tPHQV RESET High to Output ...

Page 37

Figure 13. AC Waveform for Both Page-Mode and Standard Word Read Operations VIH Address (A21-A2) VIL VIH Address (A1-A0) VIL Disable VIH CEx[E] Enable VIL VIH OE [G] VIL VIH WE [W] VIL tPHQV VOH DATA[D/Q] High Z Q0- Q15 ...

Page 38

AC Characteristics--Write Operations (1,2) Versions Symbol Parameter tPHWL (tPHEL ) RESET High Recovery to WE(CEX) Going Low tELWL (tWLEL ) CEX (WE) Low to WE(CEX) Going Low tWP Write Pulse Width tDVWH (tDVEH ) Data Setup to WE(CEX) Going High ...

Page 39

Figure 14. AC Waveform for Write Operations A VIH Address (A) VIL tAVWH (tAVEH) Disable VIH CEx,(WE)[E(W)] Enable VIL tPHWL (tPHEL) VIH OE tELWL VIL (tWLEL) Disable VIH WE,(CEx)[W(E)] Enable VIL tWP tOVWH (tDVEH) VIH DATA[D/Q] VIL VIH RESET [P] ...

Page 40

Figure 15. AC Waveform for Reset Operation VIH RESET (P) VIL Reset Specifications (1) Sym Parameter tPLPH RESET Pulse Low Time (If RESET is tied to VCC , this specification is not applicable) NOTES: 1. These specifications are valid for ...

Page 41

ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Block Erase Time Write Buffer Byte Program Time (Time to Program 16 words) Word Program Time (Using Word Program Command) Block Program Time (Using Write to Buffer Command) Block Erase/Program Cycles Note: 1.Not 100% Tested, ...

Page 42

... ORDERING INFORMATION PLASTIC PACKAGE Part NO. MX26L6419TC-10 P/N:PM0946 Access Time Package type (ns) 100/25 48-TSOP 42 MX26L6419 Cycles 100 REV. 0.3, OCT. 08, 2003 ...

Page 43

PACKAGE INFORMATION P/N:PM0946 MX26L6419 43 REV. 0.3, OCT. 08, 2003 ...

Page 44

REVISION HISTORY Revision No. Description 0 modify Package Information 0 remove deep power down mode: 1-1 power down mode:25uA(typ.) 1-2 tPHWL: 2us --> 210ns(min change VCC range: 2.7V to 3.6V --> 3.0 to 3.6V ...

Page 45

... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. MX26L6419 ...

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