LH5491U-35 Sharp, LH5491U-35 Datasheet

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LH5481 LH5491 FEATURES Fastest 64 8/9 Cascadable FIFO 35/25/15 MHz Expandable in Word Width and FIFO Depth Almost-Full/Almost-Empty and Half-Full Flags Fully Independent Asynchronous Inputs and Outputs LH5481 Output Enable forces Data Outputs to High-Impedance State Pin-Compatible Replacements for Cypress ...

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LH5481/91 INPUT SI CONTROL LOGIC IR (LH5491 DATA IN (LH5481 MASTER MR RESET PIN DESCRIPTIONS PIN PIN TYPE * DI – DI Data Inputs, LH5481 – ...

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FIFO ABSOLUTE MAXIMUM RATINGS PARAMETER Vcc Range Input Voltage Range 3 DC Output Current Storage Temperature DC Voltage Applied To Outputs In High-Z state 4 Static Discharge Voltage Power Dissipation (Package Limit) NOTES: 1. All ...

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LH5481/ TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times (10% / 90%) Input Timing Reference Levels Output Timing Reference Levels Output Load for AC Timing Tests NOTE: 1. All voltages are measured with respect to ...

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FIFO AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER f Operating Frequency O 3 HIGH Time PHSI 3 LOW Time PLSI 4 t Data Setup to SI SSI 4 t Data Hold from SI ...

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LH5481/91 OPERATIONAL DESCRIPTION Unlike earlier versions of FIFOs, the LH5481 and LH5491 use dual-port Random-Access-Memory, write and read pointers, and special control logic. The write pointer is incremented by the falling edge of the Shift In (SI) signal, while the ...

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FIFO TIMING DIAGRAMS SHIFT IN t PHSI INPUT READY t HSI DATA IN t SSI AFE (LOW NOTE: FIFO Contains 8 Words SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT (LOW) ...

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LH5481/91 TIMING DIAGRAMS (cont’d) SHIFT IN t PHSI INPUT READY t DATA IN t SSI (LOW) AFE HF *** NOTE: FIFO Contains 31 Words SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT HF (LOW) AFE **** NOTE: FIFO ...

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FIFO TIMING DIAGRAMS (cont’d) SHIFT IN t PHSI INPUT READY t HSI DATA IN t SSI (HIGH) HF AFE ***** NOTE: FIFO Contains 55 Words SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT ...

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LH5481/91 TIMING DIAGRAMS (cont’d) SHIFT OUT SHIFT IN INPUT READY DATA IN Figure 11. Bubblethrough Timing (Reading a Full FIFO) SHIFT IN SHIFT OUT OUTPUT READY DATA OUT Figure 12. Fallthrough Timing (Writing an Empty FIFO ...

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FIFO TIMING DIAGRAMS (cont’d) MASTER RESET INPUT READY OUTPUT READY SHIFT IN DATA OUT HF AFE t PMR t DIR t DOR t DSI t LXMR t DHF t DAFE Figure 13. Master Reset Timing ...

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LH5481/91 TIMING DIAGRAMS (cont’d) EMPTY 1 2 SHIFT AFE 64 63 FULL SHIFT OUT . . . HF AFE Figure 14. Shifting ...

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FIFO FIFO EXPANSION HF/AFE COMPOSITE INPUT READY ...

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... LOW until a new data word has appeared at the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. All SHARP FIFOs can be cascaded with other SHARP FIFOs of the same architecture (i.e., 64 they may not cascade with FIFOs from other manufacturers. ...

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FIFO PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300 35.00 [1.378] 34.40 [1.354] 2.54 [0.100] 0.56 [0.022] TYP. 0.36 [0.014] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28PLCC (PLCC28-P-S450) 1.22 [0.048] 1.07 [0.042 4.57 ...

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... LH5481/91 ORDERING INFORMATION LH#### X Device Type Package Examples: LH5481D-25 ( FIFO, 28-pin, 300-mil PDIP, 25 MHz) LH5491U-35 ( FIFO, 28-pin PLCC, 35 MHz Speed 15 25 Frequency (MHz 28-pin, 300-mil PDIP (DIP028-P-0300) U 28-pin Plastic Leaded Chip Carrier (PLCC28-P-S450) 5481 FIFO ...