LH28F040SUTD-Z4 Sharp, LH28F040SUTD-Z4 Datasheet
LH28F040SUTD-Z4
Related parts for LH28F040SUTD-Z4
LH28F040SUTD-Z4 Summary of contents
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... LH28F040SUTD-Z4 FEATURES • 512K × 8 Bit Configuration • Write/Erase Operation ( – V for Write/Erase at as low as 2 • Min. 2.7 V Read Capability – 190 ns Maximum Access Time ( • 2 Banks Enable the Simultaneous Read/Write/Erase Operation • 32 Independently Lockable Blocks (16K) • ...
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... LH28F040SUTD-Z4 Bank1 Bank0 OUTPUT MULTIPLEXER INPUT BUFFER Y-DECODER ADDRESS X-DECODER QUEUE LATCH ADDRESS COUNTER Figure 2. LH28F040SUTD-Z4 Block Diagram OUTPUT BUFFER DATA ID QUEUE REGISTER REGISTER CSR REGISTER DATA COMPARATOR Y GATING/SENSING . . . . . . 4M (512K × 8) Flash Memory INPUT BUFFER I/O LOGIC ...
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... V low power operation and very high read/write per- formance, the LH28040SU-Z4 is also the ideal choice for designing embedded mass storage flash memory systems. The LH28F040SUTD- very high density, high- est performance non-volatile read/write solution for solid- state storage applications. Its independently lockable 32 symmetrical blocked architecture (16K each) ...
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... Dedicated Block Write/Erase Protection • Command-Controlled Memory Protection Set/Reset Capability The LH28F040SUTD-Z4 will be available in a 40-pin, 1.2 mm thick × × TSOP (Type I) pack- age. This form factor and pinout allow for very high board layout densities. A Command User Interface (CUI) serves as the sys- tem interface between the microprocessor or micro- controller and the internal memory operation ...
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... Flash Memory The LH28F040SUTD-Z4 incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical I current 3 bank reset mode of operation is enabled when whole BE ...
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... LH28F040SUTD-Z4 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations MODE BE » 0 Bank Read Bank Output Disable X Standby V IH Bank Manufacturer ID Bank Bank Device ID Bank Bank Write Bank1 V IH NOTES: 1 ...
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... OPER. ADDRESS DATA Write X FFH Write X 90H Write X 70H Write X 50H Write X 40H Write X 10H Write X 20H Write X B0H LH28F040SUTD-Z4 SECOND BUS CYCLE NOTE OPER. ADDRESS DATA Read AA AD Read IA ID Read X CSRD Write WA WD Write WA WD Write BA D0H Write X D0H ...
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... LH28F040SUTD-Z4 LH28F040SUTD-Z4 Performance Enhancement Command Bus Definitions Following is the commands to be applied to each bank. FIRST BUS CYCLE COMMAND OPER. ADD. DATA OPER. ADD. Protect Set/Confirm Write Protect Reset/Confirm Write Lock Block/Confirm Write Bank Erase All Unlocked Blocks Write Two-Byte Write Write ...
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... Serial Write and Block Erase can not be performed in each block. However, at that time, Erase All Unlocked Block is performed normally, if used, and reflect actual LH28F040SUTD-Z4 lock status, also the unlocked block data is erased. When the device power-up or reset is completed, Set Write Protect command must be written to reflect actual block lock status ...
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... LH28F040SUTD-Z4 START WRITE 40H or 10H WRITE DATA/ADDRESS READ COMPATIBLE STATUS REGISTER 0 CSR CSR FULL STATUS CHECK IF DESIRED OPERATION COMPLETE CSR FULL STATUS CHECK PROCEDURE READ CSRD (see above) 0 DATA WRITE CSR. SUCCESSFUL LOW PP CSR.3 = DETECT 0 CLEAR CSRD RETRY/ERROR RECOVERY Figure 4. Byte Writes with Compatible Status Register 10 4M (512K × ...
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... If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5, 1. Retry Single Block Erase command. Where power off or chip reset during erase operation, 1. Clear CSR.3/4/5 and issue Reset WP command, 2. Retry Single Block Erase command. 3. Set WP command is issued, if necessary. LH28F040SUTD-Z4 COMMENTS D = 20H D0H ...
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... LH28F040SUTD-Z4 START WRITE B0H READ COMPATIBLE STATUS REGISTER 0 CSR CSR.6 = ERASE COMPLETED 1 WRITE FFH READ ARRAY DATA DONE NO READING YES WRITE D0H WRITE FFH ERASE RESUMED READ ARRAY DATA Figure 6. Erase Suspend to Read Array with Compatible Status Register 12 4M (512K × 8) Flash Memory ...
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... If CSR. set command sequence error, should be cleared before further attempts are initiated. Write FFH after the last operation to reset device to read array mode. See Command Bus Definitions for description of codes. Figure 7. Block Locking Scheme LH28F040SUTD-Z4 COMMENTS Q = CSRD Toggle ...
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... LH28F040SUTD-Z4 START RESET WP (NOTE 1) ERASE BLOCK (NOTE 2) SET WP (NOTE 3) WRITE NEW DATA TO BLOCK (NOTE 4) RELOCK BLOCK (NOTE 5) OPERATION COMPLETE FLOW TO REWRITE DATA NOTES: 1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks. 2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block. ...
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... CSR Full Status Check can be done after each 2-Byte Write, or after a sequence of 2-Byte Writes. Write FFH after the last operation to reset device to read array mode. See Command Bus Cycle notes for description of codes. LH28F040SUTD- automatically , BE ...
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... LH28F040SUTD-Z4 START (NOTE) WRITE A7H WRITE D0H READ COMPATIBLE STATUS REGISTER NO 0 SUSPEND CSR.7 = ERASE 1 CSR FULL STATUS CHECK IF DESIRED OPERATION COMPLETE CSR FULL STATUS CHECK PROCEDURE READ CSRD (see above) 0 ERASE CSR. SUCCESSFUL LOW PP CSR.3 = DETECT 0 CLEAR CSRD RETRY/ERROR ...
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... Protect command must be written to reflect the actual lock-bit status. Write FFH after the last operation to reset device to Read Array Mode. See Command Bus Cycle notes for description of codes. Figure 11. Set Write Protect LH28F040SUTD-Z4 COMMENTS Check CSR WSM Ready 0 = WSM Busy D = 57H ...
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... LH28F040SUTD-Z4 START READ COMPATIBLE STATUS REGISTER 0 CSR WRITE 47H WRITE CONFIRM DATA/ADDRESS READ COMPATIBLE STATUS REGISTER 0 CSR (NOTE) CSR. OPERATION COMPLETE 18 BUS COMMAND OPERATION Read Write Reset Write Protect Write Reset Confirm Read Read NOTE: If CSR. set command sequence error, should be cleared before further attempts are initiated ...
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... -0 0.5 CC ±30 100.0 TYP. MAX. UNITS ± 10% 2 LH28F040SUTD-Z4 UNITS TEST CONDITIONS NOTE °C Ambient Temperature 2.0 V for periods < 20 ns. CC TEST CONDITIONS NOTE T = 25° 1.0 MHz 25° 1.0 MHz ...
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... LH28F040SUTD-Z4 Timing Nomenclature For 3.3 V systems use 1.5 V cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below time (t) from BE » (E) going low (L) to the outputs (Q) becoming valid (V) CE ELQV t t time (t) from OE » ...
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... TTL: BE Inputs = MHz, I Byte/Two-Byte Serial Write Progress Block Erase in Progress Block Erase Suspended ±1 ±10 µ LH28F040SUTD-Z4 TEST CONDITIONS NOTE = V MAX GND MAX GND MAX., CC » » ± ...
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... LH28F040SUTD-Z4 DC Characteristics (Continued 3.3 V ± 0 -20°C to +70° SYMBOL PARAMETER I V Read Current PPR Write Current PPW Erase Current PPE PP V Erase Suspend PP I PPES Current V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage ...
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... MIN. MAX. 190 0 190 190 » » after the falling edge of BE » » without impact LH28F040SUTD-Z4 UNITS NOTE UNITS NOTE ns ns ...
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... LH28F040SUTD- POWER-UP STANDBY V IH ADDRESSES ( ( (NOTE ( ( HIGH-Z DATA (D/ 3 GND NOTE: BE means either DEVICE AND ADDRESS SELECTION OUTPUTS ENABLED ADDRESSES STABLE t AVAV t AVGL t GLQV t ELQV ...
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... BE must not be set low at the same time » » » » ( and WE exceeds 5 µs. Especially when you will 0 1 LH28F040SUTD-Z4 t EHRS t GHRS 3.3 V VALID t AVQV VALID 3.3 V OUTPUTS t PHQV 28F040SUZ4-16 UNITS NOTE µ ...
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... LH28F040SUTD-Z4 AC Characteristics for WE » - Controlled Command Write Operations V = 3.25 V ± 0. -20°C to +70° SYMBOL PARAMETER t Write Cycle Time AVAV t V Set Going High VPWH PP » » and BE Setup to WE Going Low ELWL Address Setup to WE Going High ...
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... WRITE VALID ADDRESS AND DATA AUTOMATED (DATA-WRITE) OR DATA-WRITE ERASE CONFIRM OR ERASE COMMAND DELAY (NOTE AVWH WHAX t t WHWL WHQV WLWH t WHDX t DVWH VPWH LH28F040SUTD-Z4 READ COMPATIBLE STATUS REGISTER DATA t WHGL t GHWL OUT IN t QVVL 28F040SUZ4-17 27 ...
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... LH28F040SUTD-Z4 AC Characteristics for BE » - Controlled Command Write Operations V = 3.25 V ± 0. -20°C to +70° SYMBOL PARAMETER t Write Cycle Time AVAV » Set VPEH PP 0 » Setup WLEL 0 » t Address Setup ...
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... WRITE VALID ADDRESS AND DATA AUTOMATED (DATA-WRITE) OR DATA-WRITE ERASE CONFIRM OR ERASE COMMAND DELAY (NOTE AVEH EHAX t t EHEL EHQV ELEH t EHDX t DVEH VPEH LH28F040SUTD-Z4 READ COMPATIBLE STATUS REGISTER DATA t EHGL t GHEL OUT IN t QVVL 28F040SUZ4-18 29 ...
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... LH28F040SUTD-Z4 Erase and Byte Write Performance V = 3.25 V ± 0. -20°C to +70° SYMBOL PARAMETER 1 t Byte Write Time WHRH 2 t Two-Byte Serial Write Time WHRH 3 t 16KB Block Write Time WHRH 4 t 16KB Block Write Time WHRH Block Erase Time (16KB) ...
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... Example: LH28F040SUT-Z4 (4M (512K x 8) Flash Memory, 190 ns, 40-pin TSOP) 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] -Z4 Speed 190 Access Time (ns) Dual Works 40-pin, 1 TSOP (Type I) (TSOP040-P-1020) 4M (512K x 8) Flash Memory LH28F040SUTD-Z4 40 0.50 [0.020] 10.20 [0.402] TYP. 9.80 [0.386] 0.25 [0.010] 0.15 [0.006] 21 1.10 [0.043] 0.90 [0.035] 1.19 0.49 [0.019] [0 ...
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... LH28F040SUTD-Z4 LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. WARRANTY SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice ...