MX29LV400TTC-90 Macronix International Co., MX29LV400TTC-90 Datasheet

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MX29LV400TTC-90

Manufacturer Part Number
MX29LV400TTC-90
Description
Manufacturer
Macronix International Co.
Datasheet

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Part Number:
MX29LV400TTC-90
Manufacturer:
MXIC/旺宏
Quantity:
20 000
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
• Fast access time: 55R/70/90ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
GENERAL DESCRIPTION
The MX29LV400T/B is a 4-mega bit Flash memory or-
ganized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV400T/B is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV400T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV400T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV400T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
P/N:PM0710
- 3.0V only operation for read, erase and program
operation
- 20mA maximum active current
- 0.2uA typical standby current
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
1
• Status Reply
• Ready/Busy pin (RY/BY)
• Sector protection
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
• Compatibility with JEDEC standard
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV400T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
- Data polling & Toggle bit for detection of program and
erase operation completion.
- Provides a hardware method of detecting program or
erase operation completion.
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
- T = Top Boot Sector
- B = Bottom Boot Sector
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP
- Pinout and software compatible with single-power
supply Flash
MX29LV400T/B
3V ONLY FLASH MEMORY
REV. 1.4, NOV. 23, 2001

Related parts for MX29LV400TTC-90

MX29LV400TTC-90 Summary of contents

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FEATURES • Extended single - supply voltage range 2.7V to 3.6V • 524,288 x 8/262,144 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55R/70/90ns • Low ...

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PIN CONFIGURATIONS 44 SOP(500 mil) 44 RESET RY/ A17 A10 A11 A12 A13 A14 A2 ...

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BLOCK STRUCTURE Table 1: MX29LV400T SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 32Kbytes 16Kwords SA8 8Kbytes ...

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BLOCK DIAGRAM CONTROL CE OE INPUT WE LOGIC RESET ADDRESS LATCH A0-A17 AND BUFFER Q0-Q15/A-1 P/N:PM0710 MX29LV400T/B PROGRAM/ERASE HIGH VOLTAGE MX29LV400T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 WRITE ...

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AUTOMATIC PROGRAMMING The MX29LV400T/B is byte programmable using the Au- tomatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming ...

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VID, as shown in table4. To verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest or- der address bit (see Table 1 and Table 2). ...

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TABLE 4. MX29LV400T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Sector Protect Word 4 555H AAH 2AAH Verify ...

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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...

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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE and OE pins to VIL the power control and selects the device the output control and gates array ...

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Flash memory. If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sysytem can thus ...

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TABLE 6. EXPANDED SILICON ID CODE Pins A0 Manufacture code Word VIL Byte VIL Device code Word VIH for MX29LV400T Byte VIH Device code Word VIH for MX29LV400B Byte VIH Sector Protection X Verification X READING ARRAY DATA The device ...

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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...

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ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector ...

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Q7, RY/BY, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Q7: Data Polling The Data Polling bit, Q7, indicates ...

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If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once ...

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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector ...

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CHIP UNPROTECT The MX29LV400T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotect mode. ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...

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Table 8. CAPACITANCE SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance READ OPERATION Table 9. DC CHARACTERISTICS - VCC = 2.7V to 3.6V (TA = ...

Page 20

AC CHARACTERISTICS TA = -40 ( Table 10. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE to Output Delay tOE OE to Output Delay tDF OE High to Output ...

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Figure 1. SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL=100pF Including jig capacitance CL=30pF for MX29LV400T/B-70 & MX29LV401T/B-70 & MX29LV400T/B-55R Figure 2. SWITCHING TEST WAVEFORMS 3.0V 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V ...

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Figure 3. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE VIL VIH OE VIL HIGH Z VOH Outputs VOL VIH RESET VIL P/N:PM0710 MX29LV400T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 22 tDF ...

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AC CHARACTERISTICS TA = -40 ( Table 11. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...

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AC CHARACTERISTICS TA = -40 ( Table 12. Alternate CE Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES ...

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Figure 4. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH Data VIL P/N:PM0710 MX29LV400T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 25 tWPH REV. ...

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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...

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Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM0710 MX29LV400T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No ...

Page 28

Figure 7. CE CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE tGHEL OE CE tWS Data tRH RESET RY/BY NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates ...

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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by DATA polling and toggle bit checking after ...

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Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM0710 MX29LV400T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H ...

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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A17 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle bit ...

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Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM0710 MX29LV400T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address ...

Page 33

Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART P/N:PM0710 MX29LV400T/B START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another ...

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Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET Control) VID VIH RESET SA, A6 A1, A0 Sector Protect or Sector Unprotect Data 60h 1us Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0. ...

Page 35

Figure 14. SECTOR PROTECT TIMING WAVEFORM(A9, OE Control 12V 3V A9 tVLHT 12V 3V OE tVLHT WE CE Data A18-A12 P/N:PM0710 MX29LV400T/B tWPP 1 tOESP Sector Address 35 Verify tVLHT 01H F0H tOE REV. 1.4, NOV. 23, 2001 ...

Page 36

Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE Control) No PLSCNT=32? Yes Device Failed P/N:PM0710 MX29LV400T/B START Set Up Sector Addr PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 150us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Addr=SA, ...

Page 37

Figure 16. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM0710 MX29LV400T/B START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector address ...

Page 38

Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM0710 MX29LV400T/B START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? Yes ...

Page 39

Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE Control) A1 12V 3V A9 tVLHT A6 12V 3V OE tVLHT WE CE Data A18-A12 Notes: tWPP1 (Write pulse width for sector protect)=100ns min, 10us(Typ.) tWPP2 (Write pulse width for sector ...

Page 40

Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0710 MX29LV400T/B START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time ...

Page 41

WRITE OPERATION STATUS Figure 20. DATA POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM0710 MX29LV400T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? No No ...

Page 42

Figure 21. TOGGLE BIT ALOGRITHM NO Program/Erase Operation Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM0710 Start Read Q7-Q0 Read Q7-Q0 ...

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Figure 22. DATA POLLING TIMINGS (DURING AUTOMATIC ALOGRITHMS) tRC Address VA tACC tCE CE tCH tOE OE tOEH WE DQ7 Q0-Q6 tBUSY RY/BY NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and ...

Page 44

Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS) tRC VA Address tACC tCE CE tCH tOE OE tOEH WE High Z Q6/Q2 tBUSY RY/BY NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...

Page 45

Table 13. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET Pulse Width (During Automatic ...

Page 46

AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE) Parameter Description JEDEC Std tELFL/tELFH CE to BYTE Switching Low or High tFLQZ BYTE Switching Low to Output HIGH Z tFHQV BYTE Switching High to Output Active Figure 25. BYTE TIMING WAVEFORM FOR READ OPERATIONS ...

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Figure 26. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from word mode to byte mode BYTE Q0~Q14 Q15/A-1 Figure 27. BYTE TIMING WAVEFORM FOR PROGRAM OPERATIONS CE WE BYTE P/N:PM0710 MX29LV400T/B tELFH DOUT (Q0-Q14) DOUT VA (Q15) ...

Page 48

Table 14. TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 28. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM 12V RESET 0 or Vcc ...

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Figure 30. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM0710 MX29LV400T/B Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. ...

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Figure 31. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A17 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q15 ...

Page 51

Table 15. ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Byte Mode Word Mode Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values ...

Page 52

... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX29LV400TMC-55R 55 MX29LV400BMC-55R 55 MX29LV400TMC-70 70 MX29LV400BMC-70 70 MX29LV400TMC-90 90 MX29LV400BMC-90 90 MX29LV400TTC-55R 55 MX29LV400BTC-55R 55 MX29LV400TTC-70 70 MX29LV400BTC-70 70 MX29LV400TTC-90 90 MX29LV400BTC-90 90 MX29LV400TXBC-55R 55 MX29LV400BXBC-55R 55 MX29LV400TXBC-70 70 MX29LV400BXBC-70 70 MX29LV400TXBC-90 90 MX29LV400BXBC-90 90 MX29LV400TXEC-55R 55 MX29LV400BXEC-55R 55 MX29LV400TXEC-70 70 P/N:PM0710 MX29LV400T/B OPERATING CURRENT STANDBY CURRENT PACKAGE MAX.(mA) MAX.(uA ...

Page 53

PART NO. ACCESS TIME (ns) MX29LV400BXEC-70 70 MX29LV400TXEC-90 90 MX29LV400BXEC-90 90 MX29LV400TMI-70 70 MX29LV400BMI-70 70 MX29LV400TMI-90 90 MX29LV400BMI-90 90 MX29LV400TTI-70 70 MX29LV400BTI-70 70 MX29LV400TTI-90 90 MX29LV400BTI-90 90 MX29LV400TXBI-70 70 MX29LV400TXBI-90 90 MX29LV400BXBI-70 70 MX29LV400BXBI-90 90 MX29LV400TXEI-70 70 MX29LV400TXEI-90 90 MX29LV400BXEI-70 ...

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PACKAGE INFORMATION 48-PIN PLASTIC TSOP P/N:PM0710 MX29LV400T/B 54 REV. 1.4, NOV. 23, 2001 ...

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PLASTIC SOP P/N:PM0710 MX29LV400T/B 55 REV. 1.4, NOV. 23, 2001 ...

Page 56

CSP (for MX29LV400TXBC/TXBI/BXBC/BXBI) P/N:PM0710 MX29LV400T/B 56 REV. 1.4, NOV. 23, 2001 ...

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CSP (for MX29LV400TXEC/TXEI/BXEC/BXEI) P/N:PM0710 MX29LV400T/B 57 REV. 1.4, NOV. 23, 2001 ...

Page 58

REVISION HISTORY Revision No. Description 1.0 Add MX29LV401T/B part number MX29LV401T/B tBUSY=90us for sector erase MX29LV400T/B tBUSY=90ns for sector erase 1.1 Correct mis-typing tOE spec of 55ns speed grade was changed from 30ns to 25ns 1.2 Separate data sheet into ...

Page 59

... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MX29LV400T O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 59 ...

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