LH52258AD-20 Sharp, LH52258AD-20 Datasheet

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LH52258AD-20

Manufacturer Part Number
LH52258AD-20
Description
CMOS 32K x 8 static RAM
Manufacturer
Sharp
Datasheet
LH52258A
FEATURES
FUNCTIONAL DESCRIPTION
organized as 32K 8. A fast, efficient design is obtained
with a CMOS periphery and a matrix constructed with
polysilicon load memory cells.
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH). Standby power (I
to its lowest level if E is raised to within 0.2 V of V
Write Enable (W) are LOW. Data is transferred from the
DQ pins to the memory location specified by the 15
address lines. The proper use of the Output Enable
control (G) can prevent bus contention.
The LH52258A is a high-speed 262,144 bit static RAM
This RAM is fully static in operation. The Chip Enable
Write cycles occur when both Chip Enable (E) and
Fast Access Times: 20/25 ns
Low-Power Standby when Deselected
TTL Compatible I/O
5 V 10% Supply
Fully-Static Operation
JEDEC Standard Pinout
Packages:
28-Pin, 300-mil DIP
28-Pin, 300-mil SOJ
SB1
) drops
CC
.
occur at the memory location specified by the address
lines. G must be brought LOW to enable the outputs.
Since the device is fully static in operation, new Read
cycles can be performed by simply changing the address.
ployed to obtain the best performance from this device.
Solid, low-impedance power and ground planes, with
high-frequency decoupling capacitors, are recom-
mended. Series termination of the inputs should be con-
sidered when transmission line effects occur.
PIN CONNECTIONS
28-PIN DIP
28-PIN SOJ
When E is LOW and W is HIGH, a static Read will
High-frequency design techniques should be em-
Figure 1. Pin Connections for DIP and
DQ
DQ
DQ
V
A
A
A
A
A
A
A
A
A
A
SS
14
12
5
4
3
2
0
7
6
0
2
1
1
CMOS 32K
SOJ Packages
10
12
13
14
11
3
4
5
6
7
8
2
9
1
24
17
16
28
27
26
25
23
22
20
19
18
15
21
DQ
DQ
DQ
DQ
A
A
A
G
A
E
DQ
V
A
W
8 Static RAM
13
8
9
11
10
CC
6
5
4
3
7
TOP VIEW
52258A-1D
1

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LH52258AD-20 Summary of contents

Page 1

LH52258A FEATURES Fast Access Times: 20/25 ns Low-Power Standby when Deselected TTL Compatible I 10% Supply Fully-Static Operation JEDEC Standard Pinout Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION The LH52258A is a high-speed 262,144 bit static ...

Page 2

LH52258A TRUTH TABLE MODE Not Selected High Selected High Read Data Out Write Data ...

Page 3

CMOS 32K 8 Static RAM ABSOLUTE MAXIMUM RATINGS PARAMETER Potential CC SS Input Voltage Range 2 DC Output Current Storage Temperature Range Power Dissipation (Package Limit) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ ...

Page 4

LH52258A AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Output Load, Timing Tests 1,2 CAPACITANCE PARAMETER C (Input Capacitance (I/O Capacitance) DQ NOTES: 1. Capacitances are maximum values ...

Page 5

CMOS 32K 8 Static RAM AC ELECTRICAL CHARACTERISTICS SYMBOL t Read Cycle Time RC t Address Access Time AA t Output Hold from Address Change Low to Valid Data Low to Output Active ELZ ...

Page 6

LH52258A TIMING DIAGRAMS – READ CYCLE Read Cycle No. 1 Chip is in Read Mode HIGH LOW and G is LOW. Read cycle timing is referenced from when all addresses are stable until the first address ...

Page 7

CMOS 32K 8 Static RAM TIMING DIAGRAMS – WRITE CYCLE Addresses must be stable during Write cycles. The outputs will remain in the High-Z state LOW when E goes LOW HIGH, the outputs will ...

Page 8

LH52258A PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300 35.00 [1.378] 34.40 [1.354] 2.54 [0.100] 0.56 [0.022] TYP. 0.36 [0.014] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28SOJ (SOJ28-P-300 18.7 [0.736] 18.3 [0.720] 0.53 [0.021] 0.33 [0.013] 1.27 [0.050] ...

Page 9

CMOS 32K 8 Static RAM ORDERING INFORMATION LH52258A Device Type Package Example: LH52258AK-25 (CMOS 32K x 8 Static RAM, 25 ns, 28-pin, 300-mil SOJ Speed 20 Access Time (ns 28-pin, 300-mil DIP (DIP28-P-300) K 28-pin, ...

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