MT9122APR Zarlink Semiconductor, MT9122APR Datasheet
MT9122APR
Related parts for MT9122APR
MT9122APR Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved. Dual Voice Echo Canceller with Tone MT9122AE MT9122AP MT9122APR MT9122AP1 MT9122APR1 28 Pin PLCC* Applications • Wireless Telephony • Trunk echo cancellers Description ...
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... Echo Canceller A and B. MT9122 CONFIG2 CONFIG1 BCLK/C4i F0i Rin 5 Rout Sin 6 Sout 7 VSS VDD 8 MCLK IC 9 F0od NLP 10 S1/DATA1 REV 11 S2/DATA2 S3/CS S4/SCLK TD1 TD2 Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet • 25 F0i Rout 24 23 Sout 22 VDD PLCC 21 F0od 20 S1/DATA1 19 S2/DATA2 ...
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... An active low selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is valid for both controller and controllerless modes. 14 PWRDN Power-down (Input): An active low resets the device and puts the MT9122 into a low-power stand-by mode. MT9122 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Data bits are clocked out following SSI or ST-BUS timing requirements. 25 F0i Frame Pulse (input): In ST-BUS operation, this is a frame alignment low going pulse. SSI operation is enabled by connecting this pin to Vss. MT9122 Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Vss. Each echo canceller in the MT9122 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. MT9122 Description Controllerless and Controller. Controllerless mode is intended for 5 Zarlink Semiconductor Inc. Data Sheet ...
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... A Rin b) Extended Delay Configuration (128ms) Optional -12dB pad PORT 2 Sin echo path Rout Optional -12dB pad Figure 3 - Device Configuration Lsin > Lrin + 20log (DTDT Zarlink Semiconductor Inc. Data Sheet PORT 2 channel A Sin + - Adaptive Filter (128 ms) channel A Rout Optional -12dB pad E.C ...
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... The NLP processor can be disabled by setting the NLPDis bit Control Register 2. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: MT9122 DTDT = hex(DTDT * 32768) (hex) (dec) TSUP = Lrin + 20log (NLPTHR) 10 NLPTHR = hex(NLPTHR * 32768) (hex) (dec) 7 Zarlink Semiconductor Inc. Data Sheet ...
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... The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2. When the PHDis bit is set to 1, G.164 tone disable requirements are selected. This applies to all four Tone Detectors. MT9122 Tone Detector TD1 Tone Detector Echo Canceller A Tone Detector TD2 Tone Detector Echo Canceller B Figure 4 - Disable Tone Detection 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Echo Canceller Functional States Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. Mute: The Mute state forces the echo canceller to transmit quiet code and halts the filter adaptation process. MT9122 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Enable Adaptation Table 2 - Functional States Control Pins (1) Filter coefficients are frozen (adaptation disabled) (2) The adaptive filter coefficients are reset to zero (3) The MT9122 cancels echo MT9122 CCITT (G.711) -Law A-Law FFh D5h Echo Canceller B S4/ Zarlink Semiconductor Inc. Data Sheet ...
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... Extended Delay Configuration: In this configuration, the two echo cancellers are internally cascaded into one 128 millisecond echo canceller. See Figure 3b. In SSI operation, ENA1 and ENA2 enable pins are used to strobe data on Rin/Sout and Sin/Rout MT9122 11 Zarlink Semiconductor Inc. Data Sheet ...
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... Mode 2. 8 bit companded PCM I/O on timeslots 2 & Mode 3. 8 bit companded PCM I/O on timeslots 2 & 3. Includes D & C chan- nel bypass in timeslots 0 & 1. Table 4 - ST-BUS Mode Select 12 Zarlink Semiconductor Inc. Data Sheet PORT2 Sin/Rout Enable Pins ENB2 ENA2 ...
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... See Figure 8. MT9122 ST-BUS Mode Selection 1 Mode 4. 16 bit 2’s complement linear PCM I/O on timeslots Table 4 - ST-BUS Mode Select Echo Canceller Table 5 - SSI Enable Strobe Pins 13 Zarlink Semiconductor Inc. Data Sheet PORT2 Sin/Rout 1 1 Port ...
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... LAW = LAW = 0 1111 1111 1000 0000 + Zero 1000 0000 1111 1111 - Zero 0000 0000 0111 1111 0111 1111 0000 0000 Table 6 - Companded PCM 14 Zarlink Semiconductor Inc. Data Sheet A-LAW LAW =1 1010 1010 1101 0101 0101 0101 0010 1010 ...
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... Set bit NLPDis disable. Set pin LAW to 1or 0 to select A-Law or µ-Law respectively. Set pin FORMAT select Sign-Magnitude or ITU-T format respectively. Set bit NBDis Control Register 2 to disable. 15 Zarlink Semiconductor Inc. Data Sheet Controller selected when pins CONFIG1 & ...
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... Set bit HPFDis Control Register 2 to disable. 1 ECB ECB Zarlink Semiconductor Inc. Data Sheet Controller selected when pins CONFIG1 & ...
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... ECA Zarlink Semiconductor Inc. Data Sheet 3 4 ECB ECB ...
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... ECA Zarlink Semiconductor Inc. Data Sheet ECB ...
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... ECB Zarlink Semiconductor Inc. Data Sheet ...
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... Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 can operate with 16 bit enable strobes. MT9122 ECA ECB bits bits bits bits ECA ECB bits bits bits bits Figure 9 - SSI Operation 20 Zarlink Semiconductor Inc. Data Sheet ...
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... Read/Write 6 bits - Addressing Data 1 bit - Unused DATA INPUT DATA OUTPUT bits - Addressing Data 1 bit - Unused 21 Zarlink Semiconductor Inc. Data Sheet ...
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... ADDRESS = 20h WRITE/READ VERIFY Bypass PAD AdaptDis ADDRESS = 01h WRITE/READ VERIFY ADDRESS = 21h WRITE/READ VERIFY NBDis HPFDis MuteS AutoTD MuteR Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 0 Power Reset Value 0 0000 0010 0 Power Reset Value 0000 0000 0 ...
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... DTDet Logic high indicates the presence of a double-talk condition. TD Logic high indicates the presence of a 2100Hz tone. MT9122 Down Conv Active TDG Zarlink Semiconductor Inc. Data Sheet ADDRESS = 02h READ ADDRESS = 22h READ Power Reset Value 0000 0000 ...
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... FIR filter. The valid 7-0 <= 128 in extended-delay mode. The default value of 7 Step Size (SS) ] where 7-0 =4, then the exponential decay start value is 512 - [NS 2-0 24 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 00h 0 Power Reset Value 00h 0 Power Reset Value ...
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... Zarlink Semiconductor Inc. Data Sheet ADDRESS = 0Dh READ ADDRESS = 2Dh READ Power Reset Value N/A 8 ADDRESS = 0Ch READ ADDRESS = 2Ch READ Power Reset Value N/A 0 ADDRESS = 0Fh READ ADDRESS = 2Fh READ Power Reset Value N/A 8 ADDRESS = 0Eh READ ...
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... ADDRESS = 1Ah WRITE/READ VERIFY ADDRESS = 3Ah WRITE/READ VERIFY Zarlink Semiconductor Inc. Data Sheet Power Reset Value 48h 8 Power Reset Value 00h 0 Power Reset Value 08h 8 Power Reset Value 00h 0 Power Reset Value 40h 8 Power Reset Value ...
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... MCLK MT9122 is in SSI mode MT9125 ADPCM MT9122 Sin Sout DSTi ADPCMo ADPCMi ENA EN1 ENB EN2 BCLK C20 Rout Rin DSTo MCLK F0i 27 Zarlink Semiconductor Inc. Data Sheet Din Dout BCLK STB1 Dual RF Section Din Dout BCLK STB1 Dual RF Section ...
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... C4i F0i MCLK MT9122 in ST-BUS mode 1 Back-To-Back Configuration using D&C channel bypass MT909x Digital Phone MT9122 Sin Sout DSTi Rout Rin DSTo F0i C4i F0i 28 Zarlink Semiconductor Inc. Data Sheet Din Dout C20 BCLK EN1 STB1 Dual RF Section Handset MCLK ...
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... 0 0. 3. 1.25 29 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 ±20 mA °C -65 150 500 mW Units Test Conditions V V 400mV noise margin V 400mV noise margin V V °C Units Conditions/Notes µ ...
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... DIH t 20 150 F0iS t 20 150 F0iH t 80 DSD t 80 ASHZ t 20 DSH t 20 DSS t 80 DFD t 200 DFW 30 Zarlink Semiconductor Inc. Data Sheet . . Test Notes ns ns MHz MHz =150pF =150pF =150pF ...
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... CSH t 100 OHZ Symbol TTL Pin MCH t MCL Figure 16 - Master Clock - MCLK 31 Zarlink Semiconductor Inc. Data Sheet Units Test Notes =150pF =150pF L CMOS Pin Units - V 0.5 0.9 0.1 ...
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... DIS DIH Bit 1 Figure 17 - SSI Data Port Timing Bit 0 Bit DSD C4H t C4L t t DSS DSH Bit 0 Bit 1 Figure 18 - ST-BUS Data Port Timing 32 Zarlink Semiconductor Inc. Data Sheet AHZ BCL SSH ASHZ V TT ...
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... TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) MT9122 DATA OUTPUT DATA INPUT t t IDH SCH t SCL Figure 19 - INTEL Serial Microport Timing t SCH t SCL 33 Zarlink Semiconductor Inc. Data Sheet ODD OHZ SCP CSH V TT ...
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... Zarlink Semiconductor 2005. All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...