W83971D Winbond, W83971D Datasheet
W83971D
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W83971D Summary of contents
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... W83971D AC'97 AUDIO CODEC ...
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... W83971D Data Sheet Revision History Pages Dates Version 1 n.a. 09/30/98 2 n.a. 01/04/99 3 All 7/16/1999 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... Mute Phone Input Mute Control.................................................................................................14 6.6.2 GN[4:0] PC Phone Input Volume Control ..................................................................................14 6.6.3 Programmable Input and Output Gain Levels............................................................................15 6.7 Mic Input Volume Control Register (Index 0Eh) ................................................................................ 16 6.7.1 Mute Mic Input Mute Control .....................................................................................................16 6.7.2 20dB Mic Boost Control ............................................................................................................16 Preliminary W83971D AC'97 AUDIO CODEC Table of Contents Publication Release Date: July 1999 - 1 - Revision A1 ...
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... MS Microphone Select ............................................................................................................20 6.15.4 LPBK Loopback Mode.............................................................................................................20 6.16 3D Control Register (Index 22h)...................................................................................................... 21 6.16.1 Depth of 3D Control Level .......................................................................................................21 6.17 Power Down and Status Register (Index 26h) ................................................................................ 21 6.17.1 PR[5:0] Power Down Mode Bits ..............................................................................................21 6.17.2 Status (READ Only) bits .........................................................................................................21 6.18 Vendor Identification Registers (Index 7Ch, 7Eh)............................................................................ 22 Preliminary W83971D Record Source Select(Right Channel) ................ ...
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... TEST MODE OPERATION..................................................................................................................... 37 11.1 ATE Test Mode:.............................................................................................................................. 37 11.2 Vendor Test Mode: ......................................................................................................................... 37 12. TYPICAL CONNECTION DIAGRAM ...................................................................................................... 38 13. HOW TO READ THE TOP MARKING ................................................................................................... 39 14. PACKAGE DIMENSIONS....................................................................................................................... 40 15. APPENDIX A: TEST REPORT ............................................................................................................... 41 16. APPENDIX B: LAYOUT GUIDE ............................................................................................................. 54 16. APPENDIX B: LAYOUT GUIDE ............................................................................................................. 55 Preliminary W83971D Publication Release Date: July 1999 - 3 - Revision A1 ...
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... The Winbond W83971D is a high performance codec compliant with Audio Codec 97 Rev1.03 requirements, in addition to 3D stereo enhancement. The definition of AC Link serial interface allows the W83971D to be used with DC97 controller as well as various digital controller which have AC Link interface. Packaged in a small 48-pin LQFP , the W83971D can be placed on the motherboard, daughter board, add-on cards, PCMCIA cards, or outside the main chassis such as in speakers ...
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... VOL M U +20dB MIC2 X SYNC BIT_CLK AC'97 Digital SDATA_OUT Interface SDATA_IN RESET# XTL_IN OSC OSC XTL_OUT Figure 3.1: W83971D Functional Block Diagram Preliminary W83971D VOL MUTE VOL MUTE VOL MUTE 3D 3D VOL MUTE VOL MUTE VOL MUTE Publication Release Date: July 1999 - 5 - MASTER ...
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... PINOUT AND PACKAGE DVdd1 1 2 XTL_IN 3 XTL_OUT 4 DVss1 5 SDATA_OUT BIT_CLK 6 DVss2 7 SDATA_IN 8 DVdd2 9 10 SYNC RESET PC_BEEP Figure 4.1: W83971D 48-pin Package and Pinout Preliminary W83971D W83971D LQFP LINE_OUT_R LINE_OUT_L AFLT2 AFLT1 Vrefout ...
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... SDATA_OUT 17 6 BIT_CLK 18 7 DVss2 19 8 SDATA_IN 20 9 DVdd2 21 10 SYNC 22 11 RESET PC_BEEP 24 Preliminary W83971D W83971D 48-LQFP Pin List SIGNAL NAME PIN# SIGNAL NAME PHONE 25 AVdd1 AUX_L 26 AVss1 AUX_R 27 Vref VIDEO_L 28 Vrefout VIDEO_R 29 AFLT1 CD_L 30 AFLT2 CD_GND 31 NC CD_R ...
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... I AUX_L I AUX_R I LINE_OUT_L O LINE_OUT_R O MONO_OUT O Preliminary W83971D DESCRIPTION AC'97 Master Reset 24.576 MHz Crystal 24.576 MHz Crystal 48 KHz Fixed Rate Sync Pulse 12.288 MHz Serial Data Clock AC'97 Serial Data Input Stream AC'97 Serial Data Output Stream DESCRIPTION PC Speaker Beep Pass Through Telephony Subsystem Speakerphone ...
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... Analog Ground AVss2 I Analog Ground DVdd1 I Digital Supply Voltage 3.3V DVdd2 I DVss1 I Digital Ground DVss2 I Digital Ground Preliminary W83971D DESCRIPTION Reference Voltage Reference Voltage Output Left Channel Anti-Aliasing Filter Capacitor Right Channel Anti-Aliasing Filter Capacitor DESCRIPTION - 9 - Publication Release Date: July 1999 Revision A1 ...
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... PR5 Control/Status 28h Reserved 7Ah Vendor Reserved 7Ch Vendor ID1 7Eh Vendor ID2 Preliminary W83971D D12 D11 D10 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ML4 ML3 ML2 ML1 ML0 ...
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... MR[5:0] Master Output (Right Channel) Volume Control These six bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -94.5dB in 1.5dB increments, providing a total of 64 programmable levels. Preliminary W83971D D10 ...
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... Output Volume Control Map MR0 MR1 Preliminary W83971D MR2 MR3 MR4 ...
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... Stereo and Mono Output Attenuation MM0 MM1 Preliminary W83971D D10 MM5 MM4 MM2 MM3 MM4 ...
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... GN[4:0] PC Phone Input Volume Control These five bits select the gain applied to the Phone Input signal. The gain is programmable from - 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . Preliminary W83971D D10 D9 D8 ...
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... Preliminary W83971D LEVEL( ...
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... GL[4:0] Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . Preliminary W83971D D10 ...
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... Video Input Control Register (Index 14h) D15 D14 D13 D12 D11 Reg# 14h Mute GL4 GL3 6.10.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled Preliminary W83971D D10 GL2 GL1 GL0 GR4 D10 D9 D8 ...
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... GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . Preliminary W83971D D10 ...
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... Record Source Select(Left Channel) SL<2:0> Left Record Source <000> Mic <001> CD_L <010> Video In_L <011> Aux In_L <100> Line In_L <101> Stereo Mix_L <110> Mono Mix <111> Phone Preliminary W83971D D10 GL2 GL1 GL0 D10 SL2 SL1 ...
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... MIX Mono Output Mode "1" : Mic Output "0" : Mono mix output 6.15.3 MS Microphone Select "1" : Microphone 2 "0" : Microphone 1 6.15.4 LPBK Loopback Mode "1" : DAC/ADC Loopback enabled "0" : DAC/ADC Loopback disabled Preliminary W83971D D10 GL2 ...
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... The power down modes controlled by each bit is described in the table below: 6.17.2 Status (READ Only) bits These bits are used to monitor the readiness of some sections of the W83971D. Reading a "1" from any of these bits would be an indication of a "ready" state. D<3:0> ...
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... The upper and lower byte of this register (index 7Ch), in conjunction with the upper byte of index register 7Eh, make up the vendor identification code for the W83971D. The Vendor ID Code (in ASCII format) is equal to WEC (Winbond Elec. Inc.,), where: F[7:0] Upper Byte (Index 7Ch) D[15: ...
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... Note: Digital Controller supports four DATA_IN pins to support one primary and three secondary codecs. BIT_CLK is an output for the primary codec and an input pin for the controller and secondary codecs. Preliminary W83971D ID1 Codec Mode NC Primary Codec ...
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... Note that the ID0 and ID1 are internally pulled up; therefore, when left floating they configure Codec as Primary. Note pull up pull down. DC '97 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 Figure 7.1: Multiple Codec Example Preliminary W83971D AC'97 ~ Primary SYNC BIT_CLK ID1 1 SDATA_OUT ID0 1 RESET# SDATA_IN AC'97 ~ Secondary #1 ...
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... Output Buffer Drive Current 8.2 AC Timing Characteristics Timing Diagrams 5.0V or 3.3V +/- 5%; AVss = DVss = 0V load A DD Cold Reset/Warm Reset Cold Reset RESET# BIT_CLK PARAMETERS RESET# active low pulse width RESET# inactive to BIT_CLK startup delay Preliminary W83971D SYMBOL MIN. TYP ...
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... Warm Reset SYNC BIT_CLK PARAMETERS SYNC active high pulse width SYNC inactive to BIT_CLK startup delay 8.3 BIT_CLK / SYNC Duty Cycle: 40/60 (worst case) BIT_CLK Tsync_high SYNC Preliminary W83971D Tsync2clk Tsync_high SYMBOL MIN. Tsync_high Tsync2clk 162.8 Tclk_low Tclk_high Tclk_period Tsync_low Tsync_period - 26 - TYP. MAX. UNITS 1 ...
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... SDATA_OUT setup to falling edge of BIT_CLK SDATA_OUT hold from falling edge of BIT_CLK SYNC setup to rising edge of BIT_CLK SYNC hold from rising edge of BIT_CLK Note: SDATA_IN setup and hold calculations determined by AC’97 Controller propagation delay Preliminary W83971D SYMBOL MIN. TYP. 12.288 Tclk_period 81 ...
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... Rise and Fall BIT_CLK, SYNC SDATA_IN, SDATA_OUT PARAMETERS BIT_CLK rise time BIT_CLK fall time SYNC rise time SYNC fall time SDATA_IN rise time SDATA_IN fall time SDATA_OUT rise time SDATA_OUT fall time Preliminary W83971D Trise Tfall SYMBOL MIN. TYP. Trise 2 Tfall 2 Trise 2 ...
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... AC_Link Low Power Mode SYNC BIT_CLK SDATA_OUT SDATA_IN PARAMETERS End of Slot 2 to BIT_CLK/SDATA_IN low Note: BIT_CLK not to scale Preliminary W83971D Slot 1 Slot 2 SYMBOL MIN. Ts2_pdown Publication Release Date: July 1999 - 29 - Ts2_pdown TYP. MAX. UNITS 1 S Revision A1 ...
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... ATE/ Vendor Test Mode RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK PARAMETERS SDATA_OUT/SYNC setup to RESET# rising edge RESET# rising edge to Hi-Z state Preliminary W83971D Tsetup2rst SYMBOL MIN. TYP. Tsetup2rst 15 Toff - 30 - Toff Hi-Z MAX. UNITS ...
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... Digital S/N: D/A A/D Total Harmonic Distortion: Line Outputs D/A & A/D Frequency Response: D/A A/D Transition Band: D/A A/D Stop Band: D/A A/D Stop Band Rejection: D/A A/D Out-of-Band Rejection: Group Delay: Power Supply Rejection Ratio: (1kHz) Preliminary W83971D SYMBOL MIN. TYP. 1.0 1.0 0.1 1.0 1 0.007 20 20 19,200 19,200 28,800 28,800 -74 -74 ...
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... A/D & D/A Frequency Response has Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-Band noise generated by DAC during normal PCM audio playback over 28.8 KHz ~ 100 KHz, with respect to 1 Vrms DAC output Preliminary W83971D SYMBOL MIN. TYP. -100 1 ...
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... Gain Error Offset Error Input Impedance D/A and Analog Outputs: Resolution Interchannel Isolation Interchannel Gain Mismatch Gain Error Gain Drift Note: Gain Error and Offset Error expressed in terms of Preliminary W83971D SYMBOL MIN MIC1, MIC2, -0.5 values Publication Release Date: July 1999 - 33 - TYP MAX UNITS 46 ...
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... Internal Clock Disable Note: Registers maintain values in sleep mode (PR4 write) and wake up with a warm reset (register values cold reset (default values). Power Down and Status Register (Index 26) read action verifies stability before powerdown write action occurs. Preliminary W83971D SYMBOL MIN. TYP. ...
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... Complete Power Down of the AC'97 device is achieved by sequential writes to the Power Down and Status Control Register (Index 26h): Normal Operation: ADC s and Input Mux: DAC s: Analog Mixer: Vrefout: AC-Link: Internal Clocks: Preliminary W83971D PR1=1 PR2=1 PR4=1 ADC’s off DAC’s off Analog off PR0 PR1 ...
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... PR0=0 PR1=0 & ADC=1 DAC=1 Figure 10.2: Power Down Procedure with Analog Section Still Active Note: To Power Up the Codec, a Warm Reset or a Cold Reset is required; PR4 is reset to zero upon either reset. Preliminary W83971D PR1=1 PR4=1 Digital I/F DAC’s off off PR1 PR4 & ...
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... TEST MODE OPERATION 11.1 ATE Test Mode: PCB In-Circuit Testing of the W83971D SDATA_OUT is sampled at the rising edge of RESET# to enter ATE test mode SDATA_IN and BIT_CLK outputs are driven to a high impedance (Hi-Z) state Note: this case never occurs during normal operation 11.2 Vendor Test Mode: Vendor test mode is entered when SYNC is sampled at the rising edge of RESET# ...
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... CD_L 1uF CD_GND 1uF CD_R 1uF MIC1 1uF MIC2 1uF LINE_IN_L 1uF LINE_IN_R Note: We suggest to use 3.3V digital power and 5.0V analog power. The performance will be better Preliminary W83971D AVDD 0.1uF 0.1uF 0.1uF 10uF 0.1uF DGND AGND 3 35 XTL_OUT LINE_OUT_L 2 36 XTL_IN ...
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... HOW TO READ THE TOP MARKING The top marking of W83781D W83971D 745AA Left: Winbond logo 1st line: Type number W83971D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 745 A A 745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision ...
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... FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Preliminary W83971D ...
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... APPENDIX A: TEST REPORT W83971D ALPHA TEST REPORT (V1.0) Features: . 16-bit stereo full-duplex codec with fixed 48KHz sampling rate . S/N ratio: 85dB (analog to analog), 75dB (analog to digital), 85dB (digital to analog) . Four analog line-level stereo inputs for connection from LINE IN, CD, VIDEO, and AUX . Two analog line-level mono inputs for speakerphone and PC BEEP ...
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... VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIXER - MONO_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: 1.2 Record . PHONE LINE_IN CD VIDEO AUX MIC STEREO MONO_MIX: ok 1.3 Attenuation and Gain . PC(DAC PC_BEEP PHONE LINE_IN CD VIDEO AUX MIC1 MIC2 + MIC: ok Preliminary W83971D ...
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... VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: 2.4 Analog Frequency Response . PC_BEEP - LINE_OUT: . PHONE - LINE_OUT: . LINE_IN - LINE_OUT LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: Preliminary W83971D pass pass pass pass pass pass pass pass pass pass pass pass pass ...
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... MIC1 - MONO_OUT: . MIC2 - MONO_OUT: D/A (Digital to Analog path) . PC(DAC) - LINE_OUT: pass A/D (Analog to Digital Record path) . PHONE: pass . LINE_IN: pass . CD: pass . VIDEO: pass . AUX: pass . MIC: pass Preliminary W83971D pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass - 44 - ...
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... Cross Talk between Inputs channels . LINE_IN - LINE_OUT LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . PC(DAC) - LINE_OUT: 2.10 Power Consumption . Analog Power Up . Analog Power Down . Digital Power Up . Digital Power Down Preliminary W83971D (Digital to Analog path) (Analog to Digital Record path) pass pass pass pass pass 21.7 mA 0 ...
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... Audio Precision Winbond W83971D A-A THD+N (LINE_IN) +0 -20 - THD+N -91dBV (L), -91dBV (R); -3dBV amplitude a-weighted. 0.003% wb_aa_line_in_thdn-3db.at2 Preliminary W83971D 01/12/99 12:03:35 10k 15k 20k ...
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... Audio Precision Winbond W83971D A-A SNR (LINE_IN) +0 -20 - SNR -92dBV (L), -92dBV (R) -60dBV amplitude a-weighted. wb_aa_line_in_snr-60db.at2 Preliminary W83971D 01/12/99 11:18:03 10k 15k 20k Hz Publication Release Date: July 1999 - 47 - Revision A1 ...
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... Audio Precision Winbond W83971D A-A Freq Response + 100 200 0dBV Frequency Response Preliminary W83971D 01/12/99 11:20:03 (LINE_IN) 500 wb_aa_line_in_fr.at2 - 10k 20k ...
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... Audio Precision Winbond W83971D A-D-A THD+N (LINE_IN) +0 -20 - THD+N -80dBV (L), -80dBV (R); -3dBV amplitude a-weighted. 0.01% wb_ada_line_in_thdn-3db.at2 Preliminary W83971D 01/12/99 12:06:04 10k 15k 20k Hz Publication Release Date: July 1999 - 49 - Revision A1 ...
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... Audio Precision Winbond W83971D A-D-A SNR (LINE_IN) +0 -20 - SNR -88dBV (L), -88dBV (R) -60dBV amplitude a-weighted. wb_ada_line_in_snr-60db.at2 Preliminary W83971D 01/12/99 11:26:55 10k 15k 20k ...
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... Audio Precision Winbond W83971D A-D-A Freq Response + 100 200 0dBV Frequency Response Preliminary W83971D 01/12/99 11:32:26 (LINE_IN) 500 wb_ada_line_in_fr.at2 Publication Release Date: July 1999 - 10k 20k Revision A1 ...
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... Audio Precision Winbond W83971D D-A THD+N (LINE_IN) +0 -20 - THD+N -83dBV (L), -83dBV (R); -3dBV amplitude a-weighted. 0.007% wb_da_line_out_thdn-3db.at2 Preliminary W83971D 01/12/99 11:56:12 10k 15k 20k ...
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... Audio Precision Winbond W83971D D-A SNR (LINE_IN) +0 -20 - SNR -85dBV (L), -85dBV -60dBV amplitude a-weighted. wb_da_line_out_snr-60db.at2 Preliminary W83971D 01/12/99 11:54:05 10k 15k 20k Hz Publication Release Date: July 1999 - 53 - Revision A1 ...
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... Audio Precision Winbond W83971D D 100 200 0dB Frequency Response Preliminary W83971D 01/12/99 12:00:02 Freq Response (LINE_IN) 500 wb_da_line_out_fr.at2 - 10k 20k ...
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... The above figure is the suggested layout for W83971D. * The decoupling capacitors should be located physically as close to the pins as possible. * The device should be located on a locally separate analog ground plane to keep noise from the digital ground return currents from modulating the W83971D" ground potential and degrading performance. Preliminary W83971D ...
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... The digital ground pins should be connected to the digital ground plane and kept separate from any of the analog ground connections and analog circuitry. * The common connection point between the two ground planes should be located near the W83971D just under the digital ground connections. ...