MX26LV800TTC-55 Macronix International Co., MX26LV800TTC-55 Datasheet
MX26LV800TTC-55
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MX26LV800TTC-55 Summary of contents
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FEATURES • Extended single - supply voltage range 3.0V to 3.6V • 1,048,576 x 8/524,288 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55/70ns • Low ...
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PIN CONFIGURATIONS 48 TSOP (Standard Type) (12mm x 20mm) A15 1 A14 2 A13 3 A12 4 A11 5 A10 WE# 11 RESET# 12 MX26LV800T RY/BY# 15 ...
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BLOCK STRUCTURE TABLE 1: MX26LV800T SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes ...
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TABLE 2: MX26LV800B SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 16Kbytes 8Kwords SA1 8Kbytes 4Kwords SA2 8Kbytes 4Kwords SA3 32Kbytes 16Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes 32Kwords SA9 ...
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BLOCK DIAGRAM CE# CONTROL OE# INPUT WE# LOGIC RESET# ADDRESS LATCH A0-A18 AND BUFFER Q0-Q15/A-1 P/N:PM1007 MX26LV800T/B PROGRAM/ERASE HIGH VOLTAGE MX26LV800T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 WRITE ...
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AUTOMATIC PROGRAMMING The MX26LV800T/B is word/byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at ...
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TABLE 3. MX26LV800T/B AUTO SELECT MODE OPERATION Description Mode CE# OE# WE# Manufacturer Code Read Device ID Word Silicon (Top Boot Block) Byte ID Device ID Word (Bottom Boot Block) Byte NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High P/N:PM1007 ...
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TABLE 4. MX26LV800T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Program Word 4 555H AAH 2AAH Byte 4 ...
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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...
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Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed ...
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TABLE 6. SILICON ID CODE Pins A0 Manufacture code Word VIL Byte VIL Device code Word VIH for MX26LV800T Byte VIH Device code Word VIH for MX26LV800B Byte VIH READING ARRAY DATA The device is automatically set to reading array ...
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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...
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Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted. Data# Polling is valid after the rising edge of the final WE# pulse in the program or ...
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After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system ...
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TABLE 7. WRITE OPERATION STATUS Status In Progress Word/Byte Program in Auto Program Algorithm Auto Erase Algorithm Exceeded Word/Byte Program in Auto Program Algorithm Time Limits Auto Erase Algorithm Note and Q2 require a valid address when reading ...
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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance TABLE 8. DC CHARACTERISTICS Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ILO Output Leakage ...
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AC CHARACTERISTICS TABLE 9. READ OPERATIONS SYMBOLPARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay tDF OE# High to Output Float (Note1) tOEH Output ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST SWITCHING TEST WAVEFORMS 3. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1007 MX26LV800T/B CL ...
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FIGURE 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1007 MX26LV800T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 22 tDF ...
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AC CHARACTERISTICS TABLE 10. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL Read ...
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AC CHARACTERISTICS TABLE 11. Alternate CE# Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...
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FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1007 MX26LV800T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 25 tWPH REV. ...
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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...
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FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No ...
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FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# tCP CE# tWS tDS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. ...
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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by DATA# polling and toggle bit checking after ...
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FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H ...
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by DATA# polling and toggle bit ...
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FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address ...
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WRITE OPERATION STATUS FIGURE 10. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1007 MX26LV800T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? No No ...
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FIGURE 11. TOGGLE BIT ALGORITHM NO Program/Erase Operation Not Complete,Write Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1007 MX26LV800T/B Start Read ...
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FIGURE 12. Data# Polling Timings (During Automatic Algorithms) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, ...
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FIGURE 13. Toggle Bit Timings (During Automatic Algorithms) tRC Address VA tACC tCE CE# tCH OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, ...
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TABLE 12. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET# Pulse Width (During Automatic ...
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AC CHARACTERISTICS TABLE 13. WORD/BYTE CONFIGURATION (BYTE#) Parameter Description JEDEC Std tELFL/tELFH CE# to BYTE# Switching Low or High tFLQZ BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active FIGURE 15. BYTE# TIMING WAVEFORM FOR ...
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FIGURE 16. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 FIGURE 17. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# WE# BYTE# P/N:PM1007 MX26LV800T/B tELFH DOUT (Q0-Q14) DOUT VA (Q15) ...
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FIGURE 18. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL ...
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TABLE 14. ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Word/Byte Mode) Erase/Program Cycles Note: 1. Not 100% tested. 2. Typical program and erase times assume the ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX26LV800TTC-55 55 MX26LV800BTC-55 55 MX26LV800TTC-70 70 MX26LV800BTC-70 70 MX26LV800TXBC-55 55 MX26LV800BXBC-55 55 MX26LV800TXBC-70 70 MX26LV800BXBC-70 70 MX26LV800TXEC-55 55 MX26LV800BXEC-55 55 MX26LV800TXEC-70 70 MX26LV800BXEC-70 70 MX26LV800TTC-55G 55 MX26LV800BTC-55G 55 MX26LV800TTC-70G 70 MX26LV800BTC-70G 70 P/N:PM1007 MX26LV800T/B OPERATING STANDBY Current MAX. (mA) Current MAX. (uA) 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 ...
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PART NO. ACCESS TIME (ns) MX26LV800TXBC-55G 55 MX26LV800BXBC-55G 55 MX26LV800TXBC-70G 70 MX26LV800BXBC-70G 70 MX26LV800TXEC-55G 55 MX26LV800BXEC-55G 55 MX26LV800TXEC-70G 70 MX26LV800BXEC-70G 70 P/N:PM1007 MX26LV800T/B OPERATING STANDBY Current MAX. (mA) Current MAX. (uA) 30 100 30 100 30 100 30 100 30 ...
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PACKAGE INFORMATION P/N:PM1007 MX26LV800T/B 44 REV. 1.3, APR. 13, 2005 ...
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CSP (for MX26LV800ATXBC/ATXBI/ABXBC/ABXBI) P/N:PM1007 MX26LV800T/B 45 REV. 1.3, APR. 13, 2005 ...
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CSP (for MX26LV800ATXEC/ATXEI/ABXEC/ABXEI) P/N:PM1007 MX26LV800T/B 46 REV. 1.3, APR. 13, 2005 ...
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REVISION HISTORY Revision No. Description 1.0 1. Modified ILI data from 1(max.) to 1(typ.)/3(max.) 2. Removed "Advanced Information" title 1.1 1. Modified the erase/program cycling to 2K cycles 2. Removed data retention table 1.2 1. Modified the erase/program cycling to ...
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... MX26LV800T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...