CXD2587Q Sony, CXD2587Q Datasheet
CXD2587Q
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CXD2587Q Summary of contents
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... CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD2587Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter ...
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... MIRR DFCT FOK SERVO DSP PWM GENERATOR FOCUS PWM FOCUS SERVO GENERATOR TRACKING PWM TRACKING GENERATOR SERVO SLED PWM SLED SERVO GENERATOR – 2 – CXD2587Q DAC Block TES1 TEST XRST RMUT LMUT XTAI Timing Logic XTAO 3rd-Order PWM AOUT1 AIN1 LOUT1 ...
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... AOUT2 RMUT 79 LMUT – 3 – CXD2587Q XTSL 36 TES1 35 TEST FRDR 33 32 FFDR TRDR 31 TFDR 30 SRDR 29 SFDR ...
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... Sled drive output. 29 SRDR Sled drive output. 30 TFDR Tracking drive output. 31 TRDR Tracking drive output. 32 FFDR Focus drive output. 33 FRDR Focus drive output — — Digital GND TEST I Test pin. Normally, GND. Description – 4 – CXD2587Q ...
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... Crystal oscillation circuit input. Master clock is externally input from this pin. 67 XTAO O Crystal oscillation circuit output — — Master clock GND — — Analog power supply AOUT1 analog output. 71 AIN1 operational amplifier input. Description ) DD – 5 – CXD2587Q ...
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... XROF is generated when the 16K RAM exceeds the ±4F jitter margin. Monitor Pin Output Combinations Command bit MTSL1 MTSL0 0 0 XUGF XPCK 0 1 MNT1 MNT0 1 0 RFCK XPCK Description Output data GFS C2PO MNT3 C2PO XROF GTOP – 6 – CXD2587Q ...
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... (2) – ( 1.5 to 3.5V – (4) – 5. – 7 – CXD2587Q = AV = 0V, Topr = –20 to +75°C) SS Applicable Typ. Max. Unit pins ...
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... V Item Symbol Min. Input amplitude V 2 5.0V ± 5 Typ. Max. Unit MHz 5.0V ± 5 Typ. Max. Unit ns 500 500 ns ns 1000 V 0 WLX V IHX V 0.9 IHX 0.1 IHX V ILX = AV = 5.0V ± 5 Typ. Max. unit V + 0.3 Vp-p DD – 8 – CXD2587Q ...
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... AV = 0V, Topr = –20 to +75° Symbol Min. Typ. Max 750 WCK t 300 SU t 300 H t 300 D t 750 Note) 750 WT t WCK – 9 – CXD2587Q Unit MHz Note) MHz ns ...
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... SCLK ••• MSB Min. Typ. Max. Unit 16 MHz 31 µ 0V, Topr = –20 to +75° Symbol Min. Typ. Max. Unit f 40 kHz COUT f 40 kHz MIRR f 5 kHz DFCTH B DD – 10 – CXD2587Q LSB Conditions ...
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... LPF external circuit diagram 768Fs/384Fs Rch RF CXD2587Q Lch ( 5.0V 0V, Topr = –20 to +75° Min. Typ. Max. 1.12 8 – 11 – CXD2587Q = 5.0V 0V 25° Min. Typ. Max. Unit 0.0050 0.0070 % 0.0045 0.0065 96 100 dB 96 100 SHIBASOKU (AM51A) Audio Analyzer ...
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... Description of Commands and Data Sets ......................................................................................... 80 §4-19. List of Servo Filter Coefficients .......................................................................................................... 95 §4-20. Filter Composition .............................................................................................................................. 97 §4-21. TRACKING and FOCUS Frequency Response .............................................................................. 104 §5. Application Circuit .................................................................................................................................. 105 Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 12 – CXD2587Q ...
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... Register Total bit length bits bits bits 7 20 bits 8 28 bits 9 24 bits A 28 bits B 16 bits C 8 bits D 16 bits E 20 bits D18 D19 D20 D21 D22 D23 – 13 – CXD2587Q 750ns or more Valid ...
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... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 26 – CXD2587Q ...
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... K47 00 NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 27 – CXD2587Q ...
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... FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS count STOP SSTP XBUSY FOK 0 GFS 0 COUT frequency division 0 OV64 0 – 28 – CXD2587Q Output data length — — — — — — 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit — — — ...
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... RXF 1 1 RXF RXF = 0 FORWARD RXF = 1 REVERSE 0.09ms 0.05ms 0.02ms 0.18ms 0.05ms 0.09ms 5.8ms 1.45ms 2.9ms Data 1 Data – 29 – CXD2587Q Data 3 Data ...
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... CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing Processing Application 1 Anti-rolling is enhanced. Sync window protection is enhanced. – 30 – CXD2587Q Data KSL3 KSL2 1 0 See the $BX commands. ...
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... Multiplier PLL VCO1 is set to high speed frequency-divided. Multiplier PLL VCO1 is set to high speed frequency-divided. Multiplier PLL VCO1 is set to high speed frequency-divided. Processing Processing Processing Processing – 31 – CXD2587Q 1 , and the output is 1 and the output is 1 and the output is 1 and the output is 1/8 ...
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... OPSL1 Data 2 D0 and subsequent data are for DF/DAC function settings. Data 3 Data 000 0 1 MCSL OPSL1 Processing Processing Processing – 33 – CXD2587Q Data ZDPL ZMUT — Data — — — ...
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... SMUT AD10 EMPH OPSL2 Data 4 Data AD5 AD4 AD3 AD2 AD1 – 34 – CXD2587Q Data Data AD0 — — — Data Data AD0 FMUT LRWO BSBST BBSL D0 — ...
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... Processing Meaning The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h 0dB to 400h. The audio output from 001h to 400h is obtained using the following equation. Audio output = 20log – – 35 – CXD2587Q Attenuation data [dB] 1024 ...
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... However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 Bass boost is on. BSBST = 0 Bass boost is off. BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 Bass boost is Max. BBSL = 0 Bass boost is Mid. BBSL can be set when OPSL2 = 1. Meaning Meaning Note) Processing Processing – 36 – CXD2587Q ...
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... C1F1 C1F2 C1 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Command bit CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. Description C2F1 C2F2 C2 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Processing – 38 – CXD2587Q ...
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... The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Symbol Command bit MTSL1 MTSL0 Output data XUGF XPCK GFS XUGF XPCK GFS MNT1 MNT0 MNT3 RFCK XPCK XROF – 39 – CXD2587Q C2PO C2PO C2PO GTOP ...
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... Peak hold at a cycle of RFCK/2 in CLVS mode Gain Gain Gain MDS1 MDS0 MDP0 Gain CLVS Gain Gain MDS0 MDS1 Data Gain CLVS See the $CX commands. Description – 40 – CXD2587Q GMDS –6dB 0dB +6dB Data ...
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... RF- CLVS PLL capture range. PLL servo mode. CLVP Automatic CLVS/CLVP switching mode. CLVA Used for normal playback. BRAKE Z MDP L BRAKE n · 236 (ns – 41 – CXD2587Q Data Data ...
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... Subcode Interface In the CXD2587Q, only SubQ can be readout. The subcodes P and cannot be readout. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. § ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 3-1. The CXD2587Q has a built-in three-stage PLL. • The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL. • The second-stage PLL is a digital PLL that regenerates the actual channel clock. ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD2587Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. • The correction status can be monitored externally. See Table 3-2. ...
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... Dependent on error condition MNT3 C1 correction MNT1 MNT0 §3-4. DA Interface • The CXD2587Q's DA interface is as follows: Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. C2 correction Strobe – 47 – CXD2587Q ...
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... CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD2587Q during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µ ...
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... FZC after FZC has been continuously high for a longer time than E. Auto focus Focus search up FOK = H NO YES (Check whether FZC is continuously high for the period of time E set with register 5.) FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 3-6-(a). Auto Focus Flow Chart – 50 – CXD2587Q ...
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... Blind E Fig. 3-6-(b). Auto Focus Timing Chart tracks. COUT is used for counting the number of jumps. The N-track move – 51 – CXD2587Q $08 tracks, note that the 16 ...
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... Fig. 3-7-(b). 1-Track Jump Timing Chart Track (REV kick for Track FWD kick sled servo OFF REV jump) WAIT (Blind A) COUT = NO YES (FWD kick for Track REV kick REV jump) WAIT (Brake B) Track, sled servo ON END Brake B $2C ($28) – 52 – CXD2587Q $25 ...
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... Fig. 3-8-(b). 10-Track Jump Timing Chart 10 Track Track, sled FWD kick WAIT (Blind A) COUT = (Counts COUT 5) YES Track, REV kick C = Overflow ? NO (Check whether the COUT cycle is longer than overflow C.) YES Track, sled servo ON END COUT 5 count $2E ($2B) – 53 – CXD2587Q Overflow C $25 ...
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... COUT N count Command for DSSP $2A ($2F) Fig. 3-9-(b). 2N-Track Jump Timing Chart 2N Track Track, sled FWD kick WAIT (Blind A) COUT = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Overflow C $2E ($2B) $26 ($27) – 54 – CXD2587Q Kick D $25 ...
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... Fig. 3-10-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLAT COUT BUSY Blind A Command for $22 ($23) DSSP Fig. 3-10-(b). N-Track Move Timing Chart N Track move Track servo OFF Sled FWD kick WAIT (Blind A) COUT = N NO YES Track, sled servo OFF END END COUT N count – 55 – CXD2587Q $20 ...
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... MDS 1/2 MUX CLV P/S Oversampling Filter-2 Noise Shape Modulation MDP CLVS U/D : Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo Fig. 3-11. Block Diagram – 56 – CXD2587Q MDP Error Measure Filter-1 Gain MDP ...
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... CD-DSP Block Playback Speed In the CXD2587Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X. CD-DSP block playback speed Crystal XTSL DSPB 768Fs 0 768Fs 1 768Fs 1 384Fs 0 384Fs 0 384Fs 44.1kHz speed playback, the timer value for the auto sequence is halved. ...
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... Y3 (Y1 > Y3 > Y2). First sent, followed by X2 sent before X1 reaches the figure), X1 continues approaching Y2. Next sent before X1 reaches the figure), X1 then approaches Y3 from the value ( the figure) at that point. 0dB 3FF ( – 000 (H) 23.2 [ms] – 58 – CXD2587Q ...
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... When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $ Soft mute on 23.2 [ms] – 59 – CXD2587Q Soft mute off 23.2 [ms] ...
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... Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 3-12 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14. 100 300 1k 3k Digital Bass Boost Frequency Response [Hz] Graph 3-12. – 60 – CXD2587Q Normal DBB MID DBB MAX 10k 30k ...
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... LPF Block The CXD2587Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency determined flexibly. The reference voltage ( ( The LPF block application circuit is shown below. ...
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... Asymmetry Compensation Fig. 3-14 shows the block diagram and circuit example. R1 RFAC R1 BIAS Fig. 3-14. Asymmetry Compensation Application Circuit CXD2587Q ASYO R1 R2 ASYI – 62 – CXD2587Q ...
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... LSB first. • Data which can be stored in the LSI is 1 packet (4 packs). Subcode Decoder Fig. 3-15. Block Diagram of CD TEXT Demodulation Circuit CD TEXT Decoder SQCK SQSO TXOUT – 63 – CXD2587Q ...
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... MCK = 128Fs) Input range: 0.3V DD Output format: 7-bit PWM Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 0.43V DD Other: RF zero level automatic measurement – 65 – CXD2587Q : Supply voltage) DD ...
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... AVRG (Average) Measurement and Compensation The CXD2587Q has a circuit that measures the averages of RFDC, VC, FE and TE and a circuit that compensates these signals to control the servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2587Q, and is able to cancel the offset ...
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... The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register. • FLC1 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register. • FLC0 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register. – 67 – CXD2587Q ...
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... The number of steps by which the count value changes can be selected from steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 A: Register mode B: Counter mode C: Counter mode (when stopped) – 68 – CXD2587Q V 0.4. DD ...
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... The default settings aim for 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. Max. 11.4µs Timing Chart 4-4. – 70 – CXD2587Q AGCNTL completion ...
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... AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2587Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0 ...
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... FOCUS SERVO OFF, 0V OUT 0 0 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP Table 4-6. $02 $03 and performing only FCS search operation. $00 $02 $03 FCSDRV RF FOK FE 0 FZC – 72 – CXD2587Q : Don’t care $08 Fig. 4-8. ...
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... In addition, when the TRK servo is on and D17 set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD2587Q has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 4-17.) SLD Servo ...
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... Fig. 4-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 – Peak Hold1 DFCT MIRR Comp (Mirror comparator level Fig. 4-11. SDF (Defect comparator level Fig. 4-12. – 74 – CXD2587Q ...
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... SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $ Anti Shock TE Filter TRK Gain Up Filter TRK Gain Normal Filter Hold Filter DFCT Servo Filter Fig. 4-13. ATSK Comparator TRK PWM Gen Fig. 4-14. – 75 – CXD2587Q Hold register EN SENS ...
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... ANTI SHOCK ANTI SHOCK OFF 1 BRAKE ON 0 BRAKE OFF TRACKING GAIN NORMAL 0 TRACKING GAIN TRACKING GAIN UP FILTER SELECT 1 0 TRACKING GAIN UP FILTER SELECT 2 Fig. 4-17. – 76 – CXD2587Q Outer track Inner track FWD Servo ON JMP Fig. 4-16. : Don’t care ...
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... SCLK t SCLK pulse width SPW t Delay time DLS Table 4-19. During readout, the upper 8 bits of the command register must be 39 (Hex). t SPW ••• 1/f SCLK MSB ••• Fig. 4-18. Typ. Max. Unit Min. MHz 16 31.3 ns µs 15 – 77 – CXD2587Q LSB ...
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... TFDR MCK 2 2 FRDR/ TRDR 180ns MCK 5.6448MHz Output value –A 64t MCK At MCK 32t 32t 32t MCK MCK t MCK MCK MCK 2 2 Timing Chart 4-20. – 78 – CXD2587Q Output value 0 64t MCK 32t 32t MCK MCK MCK ...
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... Example of Driver Circuit 22k RDR FDR 22k 22k 22k Fig. 4-21. Driver Circuit – 79 – CXD2587Q V CC DRV V EE ...
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... The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. – 80 – CXD2587Q ...
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... FB9 FB8 FB7 FB6 FB5 V /5 respectively D10 TV9 TV8 TV7 TV6 TV5 V – 81 – CXD2587Q — FB4 FB3 FB2 FB1 — and DD : supply voltage ...
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... preset PWM driver supply voltage PWM driver supply voltage D10 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 PWM driver supply voltage – 82 – CXD2587Q ...
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... AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) D10 0. supply voltage); FE input conversion DD DD Slice level 1/4 V 0.4 DD 1/8 V 0.4 DD 1/16 V 0.4 DD 1/ preset PWM driver supply voltage FE/TE input conversion 1/32 V 0.4 DD 1/16 V 0.4 DD 1/16 V 0.4 DD 1 preset – 83 – CXD2587Q ...
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... TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with All commands are on when set to 1. D10 are accepted every 2.9ms. (when MCK = 128Fs) – 84 – CXD2587Q ...
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... RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) – (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal – 85 – CXD2587Q Readout data length 8 bits 16 bits 8 bits $399F $399E 8 bits $399D 9 bits $399C 9 bits ...
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... Relative gain TPS1 0dB 0 +6dB 0 +12dB 1 +18dB 1 – 86 – CXD2587Q SJHD INBK MTI0 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1 ...
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... V 0. 32/256 V 0. 40/256 V 0. 48/256 V 0. 50/256 V 0. preset V 1.14V) DD Slice level 0.0156 V 1.14 DD 0.0234 V 1.14 DD 0.0313 V 1.14 DD 0.0391 V 1. supply voltage DD DFCT maximum time No timer limit 2.00ms 2.36 2.72 – 87 – CXD2587Q ...
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... This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK. V 1.14V/ms, 44.1kHz) DD Count-down speed [V/ms] [kHz] 0.0431 V 1.14 22.05 DD 0.0861 V 1.14 44.1 DD 0.172 V 1.14 88.2 DD 0.344 V 1.14 176 preset supply voltage DD 1.14V/ms, 352.8kHz) DD Count-down speed [V/ms] [kHz] 0.344 V 1.14 176.4 DD 0.688 V 1.14 352.8 DD 1.38 V 1.14 705.6 DD 2.75 V 1.14 1411 preset supply voltage DD – 88 – CXD2587Q ...
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... BTS1 BTS0 MRC1 MRC0 TZC STZC HPTZC DTZC COUT pin output STZC HPTZC COUT : preset, —: don't care – 89 – CXD2587Q MRC1 MRC0 Setting time [µ 5.669 0 1 11.338 1 0 22.675 ...
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... TRK filter SLD filter OFF OFF OFF Tracking zero level correction TRK filter SLD filter OFF OFF OFF VC level correction TRK filter SLD filter OFF OFF OFF : preset, — : Don't care – 90 – CXD2587Q ...
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... Please refer also to §4-20. Filter Composition. Positive output coefficient TRK Filter Positive output coefficient SLD Filter Positive output coefficient TRK Hold Filter Positive output coefficient TRK Filter M0D Positive output coefficient SLD Filter Positive output coefficient TRK Hold Filter – 91 – CXD2587Q ...
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... D10 MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. – 92 – CXD2587Q LKIN COIN MDFI MIRI XT1D : preset, —: don't care ...
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... V 0 1/ 1 preset XT4D Frequency division ratio 0 According to XTSL — 1/1 — 1/2 1 1/4 – 93 – CXD2587Q AGHF ASOT These settings are the same for both focus auto gain control and tracking auto gain control. : preset, —: don't care ...
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... Serial data input D/A Analog output Clock input Latch enable input Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. – 94 – CXD2587Q · · · · · · MSB · · · LSB LSB To the 7-segment LED To the 7-segment LED MSB To an oscilloscope, etc ...
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... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 95 – CXD2587Q ...
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... K47 00 NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 96 – CXD2587Q ...
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... FCS K2B Hold Reg 1 M05 –1 Z K28 K2A –7 – K29 Note) Set the MSB bit of the K27 and K29 coefficients to 0. – 97 – CXD2587Q FCS AUTO Gain M06 M07 K11 K13 –1 Z K10 7 2 FCS PWM FCS SRCH FCS ...
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... K1E K20 –7 – K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. M0E M0F K3E –1 Z K3D – 98 – CXD2587Q TRK AUTO Gain M0E M0F K22 K23 –1 Z K21 7 2 TRK PWM TRK JMP TRK AUTO Gain ...
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... K03 –7 – K02 K04 Note) Set the MSB bit of the K02 and K04 coefficients to 0. Slice M09 –1 Z K14 K15 – 99 – CXD2587Q TRK AUTO Gain M0E M0F K3E K23 –1 Z K3D 7 2 TRK PWM TRK JMP TRK AUTO Gain – ...
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... M10 M11 –1 Z K49 K4B –7 – K4A K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 100 – CXD2587Q M0A Anti Shock Comp K35 Reg –1 Z K33 K34 AVRG Reg M19 TRK K45 Hold Reg – ...
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... K0D K0E FCS K2B Hold Reg 1 M05 –1 Z K28 80H –7 –7 – K29 K2A – 101 – CXD2587Q FCS AUTO Gain M06 M07 K11 K13 –1 Z K10 7 2 FCS PWM FCS SRCH FCS AUTO Gain M06 M07 K2D K13 – ...
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... M0D Z –1 K1E 80H –7 –7 – K1F K20 M0E K3E –1 Z K3D 2 –7 – 102 – CXD2587Q TRK AUTO Gain M0E M0F K22 K23 Z –1 K21 7 2 TRK PWM TRK JMP TRK AUTO Gain 7 2 M0F K23 TRK PWM ...
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... Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. M0D –1 Z K3A 80H –7 –7 – K3B K3C – 103 – CXD2587Q TRK AUTO Gain M0E M0F K3E K23 –1 Z K3D 7 2 TRK PWM TRK JMP ...
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... NORMAL GAIN UP 10 100 1K f – Frequency [Hz] FOCUS frequency response NORMAL GAIN DOWN 10 100 1K f – Frequency [Hz] – 104 – CXD2587Q 180° 90° G 0° –90° –180° 20K 180° 90° G 0° –90° –180° 20K ...
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... – 105 – CXD2587Q DD DD ...
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... SONY CODE QFP-80P-L03 EIAJ CODE QFP080-P-1414 JEDEC CODE 80PIN QFP (PLASTIC 0.15 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 106 – CXD2587Q + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 0.1 + 0.15 0.1 – 0.1 0° to 10° EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g ...