ATMEGA8515L ATMEL Corporation, ATMEGA8515L Datasheet

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ATMEGA8515L

Manufacturer Part Number
ATMEGA8515L
Description
Manufacturer
ATMEL Corporation
Datasheet

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Features
High-performance, Low-power AVR
RISC Architecture
Nonvolatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 8K Bytes of In-System Self-programmable Flash
– Optional Boot Code Section with Independent Lock bits
– 512 Bytes EEPROM
– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-down and Standby
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515
– 0 - 8 MHz for ATmega8515L
– 0 - 16 MHz for ATmega8515
Mode
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
®
8-bit Microcontroller
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega8515
ATmega8515L
Rev. 2512G–AVR–03/05
2512G–AVR–03/05

Related parts for ATMEGA8515L

ATMEGA8515L Summary of contents

Page 1

... Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515 • Speed Grades – MHz for ATmega8515L – MHz for ATmega8515 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System ...

Page 2

Pin Configurations Figure 1. Pinout ATmega8515 TQFP/MLF (MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7 (INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11 ATmega8515(L) 2 ...

Page 3

Overview Block Diagram 2512G–AVR–03/05 The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the sys- ...

Page 4

Disclaimer AT90S4414/8515 and ATmega8515 Compatibility AT90S4414/8515 Compatibility Mode ATmega8515(L) 4 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent ...

Page 5

Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 2512G–AVR–03/05 Digital supply voltage. Ground. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for ...

Page 6

About Code Examples ATmega8515(L) 6 This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not ...

Page 7

AVR CPU Core Introduction Architectural Overview 2512G–AVR–03/05 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...

Page 8

ALU – Arithmetic Logic Unit ATmega8515(L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be ...

Page 9

Status Register 2512G–AVR–03/05 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated ...

Page 10

General Purpose Register File ATmega8515(L) 10 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit ...

Page 11

The X-register, Y-register, and Z-register Stack Pointer 2512G–AVR–03/05 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, ...

Page 12

Instruction Execution Timing Reset and Interrupt Handling ATmega8515(L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. ...

Page 13

Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 164. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all ...

Page 14

Interrupt Response Time ATmega8515(L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example ; set global interrupt enable sei sleep ; ...

Page 15

AVR ATmega8515 Memories In-System Reprogrammable Flash Program memory 2512G–AVR–03/05 This section describes the different memories in the ATmega8515. The AVR architec- ture has two main memory spaces, the Data Memory and the Program memory space. In addition, the ATmega8515 features ...

Page 16

SRAM Data Memory ATmega8515(L) 16 Figure 9 shows how the ATmega8515 SRAM Memory is organized. The lower 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register ...

Page 17

Data Memory Access Times 2512G–AVR–03/05 Figure 9. Data Memory Map Data Memory 32 Registers 64 I/O Registers Internal SRAM (512 x 8) External SRAM (0 - 64K x 8) This section describes the general access timing concepts for internal memory ...

Page 18

EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL ATmega8515(L) 18 The ATmega8515 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read ...

Page 19

The EEPROM Data Register – EEDR The EEPROM Control Register – EECR 2512G–AVR–03/05 Bit MSB Read/Write R/W R/W R/W Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the ...

Page 20

ATmega8515(L) 20 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or ...

Page 21

Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; ...

Page 22

EEPROM Write During Power- down Sleep Mode ATmega8515(L) 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ...

Page 23

Preventing EEPROM Corruption I/O Memory 2512G–AVR–03/05 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the ...

Page 24

External Memory Interface Overview Using the External Memory Interface ATmega8515(L) 24 With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals ...

Page 25

Address Latch Requirements 2512G–AVR–03/05 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When the ...

Page 26

Pull-up and Bus Keeper Timing ATmega8515(L) 26 The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port Register is written to one. To reduce power consumption in sleep mode recom- mended to disable the ...

Page 27

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. Addr. DA7:0 Prev. Data WR DA7:0 (XMBK = 0) Prev. Data DA7:0 (XMBK = 1) Prev. ...

Page 28

XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR ATmega8515(L) 28 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = System Clock (CLK ) CPU ALE A15:8 Prev. ...

Page 29

SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits. Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 SRL1 SRL0 ...

Page 30

Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB ATmega8515(L) 30 Bit – XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 6 – XMBK: External ...

Page 31

Figure 17. Address Map with 32 KB External Memory Memory Configuration AVR Memory Map 0x0000 Internal Memory 0x025F 0x0260 External 0x7FFF 0x8000 Memory 0x825F 0x8260 (Unused) 0xFFFF ATmega8515(L) External 32K SRAM 0x0000 0x025F 0x0260 0x7FFF 31 ...

Page 32

Using all 64KB Locations of External Memory ATmega8515(L) 32 Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only 64,928 bytes of External Memory is available by default (address space 0x0000 to 0x025F is ...

Page 33

System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O 2512G–AVR–03/05 Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not ...

Page 34

Flash Clock – clk FLASH Clock Sources Default Clock Source Crystal Oscillator ATmega8515(L) 34 The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. The device has the following clock ...

Page 35

Some initial guidelines for choosing capacitors for use with crystals are given in Table 7. For ceramic resonators, the capacitor values given by the ...

Page 36

Low-frequency Crystal Oscillator ATmega8515(L) 36 Table 8. Start-up Times for the Crystal Oscillator Clock Selection (Continued) Start-up Time CKSEL0 SUT1..0 from Power-down 1 01 16K 16K 16K CK Notes: 1. These options should only ...

Page 37

External RC Oscillator 2512G–AVR–03/05 For timing insensitive applications, the external RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the ...

Page 38

Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL ATmega8515(L) 38 The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25qC. This clock may be selected ...

Page 39

External Clock 2512G–AVR–03/05 will increase the frequency of the internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not ...

Page 40

Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR ATmega8515(L) 40 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep ...

Page 41

Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode 2512G–AVR–03/05 Bit SM0 SRL2 SRL1 Read/Write R/W R/W R/W Initial Value • Bits 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode ...

Page 42

Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer ATmega8515(L) 42 When the SM2..0 bits are written to 110, and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby ...

Page 43

Port Pins 2512G–AVR–03/05 When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk ) ...

Page 44

System Control and Reset Resetting the AVR Reset Sources ATmega8515(L) 44 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must ...

Page 45

... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega8515L and BODLEVEL=0 for ATmega8515. BODLEVEL=1 is not applicable for ATmega8515. ATmega8515(L) ...

Page 46

Power-on Reset ATmega8515( Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 18. The POR is activated whenever V detection level. The POR circuit can be used to ...

Page 47

External Reset Brown-out Detection 2512G–AVR–03/05 An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 18) will generate a reset, even if the clock is not running. ...

Page 48

Watchdog Reset MCU Control and Status Register – MCUCSR ATmega8515(L) 48 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts ...

Page 49

Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer 2512G–AVR–03/05 ATmega8515 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator. The ...

Page 50

Watchdog Timer Control Register – WDTCR ATmega8515(L) 50 Table 20. WDT Configuration as a Function of the Fuse Settings of S8515C and WDTON. S8515C WDTON Unprogrammed Unprogrammed Unprogrammed Programmed Programmed Unprogrammed Programmed Programmed Figure 28. Watchdog Timer WATCHDOG OSCILLATOR Bit ...

Page 51

In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock ...

Page 52

Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 ATmega8515(L) 52 The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. ...

Page 53

Interrupts Interrupt Vectors in ATmega8515 2512G–AVR–03/05 This section describes the specifics of the interrupt handling as performed in ATmega8515. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 22. Reset ...

Page 54

ATmega8515(L) 54 Table 23. Reset and Interrupt Vectors Placement BOOTRST IVSEL Reset Address 1 0 $0000 1 1 $0000 0 0 Boot Reset Address 0 1 Boot Reset Address Note: 1. The Boot Reset Address is shown in Table 78 ...

Page 55

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset ...

Page 56

Moving Interrupts between Application and Boot Space General Interrupt Control Register – GICR ATmega8515(L) 56 $C12 out SPH,r16 $C13 ldi r16,low(RAMEND) $C14 out SPL,r16 $C15 sei $C16 <instr> The General Interrupt Control Register controls the placement of the Interrupt Vector ...

Page 57

Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL ...

Page 58

I/O Ports Introduction ATmega8515(L) 58 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other ...

Page 59

Ports as General Digital I/O Configuring the Pin 2512G–AVR–03/05 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 30. General Digital I/O Pxn ...

Page 60

Reading the Pin Value ATmega8515(L) 60 enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the ...

Page 61

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure ...

Page 62

Digital Input Enable and Sleep Modes ATmega8515(L) 62 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups ...

Page 63

Unconnected pins Alternate Port Functions 2512G–AVR–03/05 If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, ...

Page 64

ATmega8515(L) 64 Table 25 summarizes the function of the overriding signals. The pin and port indexes from Figure 33 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. ...

Page 65

Special Function IO Register – SFIOR Alternate Functions of Port A 2512G–AVR–03/05 Bit – XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written ...

Page 66

Alternate Functions Of Port B ATmega8515(L) 66 Table 28. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AD3 PA2/AD2 PUOE SRE SRE PUOV ~(WR | ADA) • ~(WR | ADA) • PortA3 PortA2 DDOE SRE SRE DDOV WR | ...

Page 67

MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. ...

Page 68

ATmega8515(L) 68 Table 30. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE ...

Page 69

Alternate Functions of Port C 2512G–AVR–03/05 The Port C pins with alternate functions are shown in Table 32. Table 32. Port C Pins Alternate Functions Port Pin Alternate Function PC7 A15 (External memory interface address bit 15) PC6 A14 (External ...

Page 70

ATmega8515(L) 70 Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/A15 PUOE SRE • (XMM<1) PUOV 0 DDOE SRE • (XMM<1) DDOV 1 PVOE SRE • (XMM<1) PVOV A15 DIEOE 0 DIEOV 0 DI – AIO – ...

Page 71

Alternate Functions of Port D 2512G–AVR–03/05 The Port D pins with alternate functions are shown in Table 35. Table 35. Port D Pins Alternate Functions Port Pin Alternate Function PD7 RD (Read Strobe to External Memory) PD6 WR (Write Strobe ...

Page 72

ATmega8515(L) 72 Table 36 and Table 37 relate the alternate functions of Port D to the overriding signals shown in Figure 33 on page 63. Table 36. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/RD PD6/WR PUOE SRE SRE ...

Page 73

Alternate Functions of Port E 2512G–AVR–03/05 The Port E pins with alternate functions are shown in Table 38. Table 38. Port E Pins Alternate Functions Port Pin Alternate Function PE2 OC1B (Timer/Counter1 Output Compare B Match Output) PE1 ALE (Address ...

Page 74

Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B ...

Page 75

Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...

Page 76

External Interrupts MCU Control Register – MCUCR ATmega8515(L) 76 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature ...

Page 77

Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR 2512G–AVR–03/05 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on ...

Page 78

General Interrupt Flag Register – GIFR ATmega8515(L) 78 corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter- rupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) ...

Page 79

Timer/Counter0 with PWM Overview Registers 2512G–AVR–03/05 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator ...

Page 80

Definitions Timer/Counter Clock Sources Counter Unit ATmega8515(L) 80 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T0 The double buffered Output Compare Register (OCR0) is compared ...

Page 81

Output Compare Unit 2512G–AVR–03/05 clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, ...

Page 82

Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATmega8515(L) 82 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare ...

Page 83

Compare Match Output Unit Compare Output Mode and Waveform Generation 2512G–AVR–03/05 The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. ...

Page 84

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8515(L) 84 The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) ...

Page 85

Fast PWM Mode 2512G–AVR–03/05 when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is ...

Page 86

ATmega8515(L) 86 Figure 39. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be ...

Page 87

Phase Correct PWM Mode 2512G–AVR–03/05 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from ...

Page 88

Timer/Counter Timing Diagrams ATmega8515(L) 88 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The N variable represents the prescale factor (1, ...

Page 89

Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting ...

Page 90

Timer/Counter Register Description Timer/Counter Control Register – TCCR0 ATmega8515(L) 90 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only ...

Page 91

When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 45 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). ...

Page 92

Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega8515(L) 92 Table 48. Clock Select Bit Description CS02 CS01 CS00 Description clk /64 (From prescaler) ...

Page 93

TOV1 OCF1A OCF1B Read/Write R/W R/W R/W Initial Value • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing ...

Page 94

Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega8515(L) 94 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The ...

Page 95

Special Function IO Register – SFIOR 2512G–AVR–03/05 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock frequency ...

Page 96

Timer/Counter1 Overview ATmega8515(L) 96 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare ...

Page 97

Registers 2512G–AVR–03/05 Figure 47. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 66, and Table 35 on page 71 for ...

Page 98

Definitions Compatibility ATmega8515(L) 98 also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either ...

Page 99

Accessing 16-bit Registers 2512G–AVR–03/05 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...

Page 100

ATmega8515(L) 100 The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; ...

Page 101

Reusing the Temporary High Byte Register 2512G–AVR–03/05 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) ...

Page 102

Timer/Counter Clock Sources Counter Unit ATmega8515(L) 102 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located ...

Page 103

Input Capture Unit 2512G–AVR–03/05 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 108. The Timer/Counter Overflow (TOV1) Flag is set according ...

Page 104

Input Capture Trigger Source Noise Canceler Using the Input Capture Unit ATmega8515(L) 104 byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register ...

Page 105

Output Compare Units 2512G–AVR–03/05 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the ...

Page 106

Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit ATmega8515(L) 106 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but ...

Page 107

Compare Match Output Unit 2512G–AVR–03/05 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the ...

Page 108

Compare Output Mode and Waveform Generation Modes of Operation Normal Mode ATmega8515(L) 108 The Waveform Generator uses the COM1x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that ...

Page 109

Clear Timer on Compare Match (CTC) Mode 2512G–AVR–03/05 In clear timer on compare or CTC mode (WGM13 12), the OCR1A or ICR1 Reg- ister are used to manipulate the counter resolution. In CTC mode the counter is ...

Page 110

Fast PWM Mode ATmega8515(L) 110 The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options ...

Page 111

TOP and com- pare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of ...

Page 112

Phase Correct PWM Mode ATmega8515(L) 112 The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode ...

Page 113

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock ...

Page 114

Phase and Frequency Correct PWM Mode ATmega8515(L) 114 The phase and frequency correct Pulse Width Modulation, or phase and frequency cor- rect PWM mode (WGM13 provides a high resolution phase and frequency correct PWM waveform generation ...

Page 115

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the ...

Page 116

Timer/Counter Timing Diagrams ATmega8515(L) 116 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x ...

Page 117

Figure 58. Timer/Counter Timing Diagram, No Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old ...

Page 118

Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A ATmega8515(L) 118 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • ...

Page 119

Table 52. Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13 14: Toggle OC1A on Compare Match, OC1B ...

Page 120

Table 53. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

Page 121

Timer/Counter1 Control Register B – TCCR1B 2512G–AVR–03/05 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input ...

Page 122

Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL ATmega8515(L) 122 Bit Read/Write R/W R/W R/W Initial Value The two ...

Page 123

Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK 2512G–AVR–03/05 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each ...

Page 124

Timer/Counter Interrupt Flag (1) Register – TIFR ATmega8515(L) 124 Bit TOV1 OCF1A OC1FB Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are ...

Page 125

Serial Peripheral Interface – SPI 2512G–AVR–03/05 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8515 and peripheral devices or between several AVR devices. The ATmega8515 SPI includes the following features: • Full Duplex, 3-wire Synchronous Data ...

Page 126

ATmega8515(L) 126 When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data ...

Page 127

The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, ...

Page 128

ATmega8515(L) 128 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) ldi DDR_SPI,r17 out ; ...

Page 129

SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR 2512G–AVR–03/05 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO ...

Page 130

ATmega8515(L) 130 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is ...

Page 131

SPI Status Register – SPSR SPI Data Register – SPDR 2512G–AVR–03/05 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is ...

Page 132

Data Modes ATmega8515(L) 132 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 62 and Figure 63. ...

Page 133

USART Single USART 2512G–AVR–03/05 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...

Page 134

ATmega8515(L) 134 Figure 64. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 37 on page 72, and Table 31 on ...

Page 135

AVR USART vs. AVR UART – Compatibility Clock Generation 2512G–AVR–03/05 The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver ...

Page 136

Internal Clock Generation – The Baud Rate Generator ATmega8515(L) 136 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK ...

Page 137

Double Speed Operation (U2X) External Clock Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock 2512G–AVR–03/05 The transfer rate can be doubled by setting the U2X bit in UCSRA. ...

Page 138

Frame Formats Parity Bit Calculation ATmega8515(L) 138 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations ...

Page 139

USART Initialization 2512G–AVR–03/05 If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The USART has to be initialized before any communication can take place. The initial- ization process normally ...

Page 140

Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8515(L) 140 More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a ...

Page 141

Sending Frames with 9 Data Bits Transmitter Flags and Interrupts 2512G–AVR–03/05 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written ...

Page 142

Parity Generator Disabling the Transmitter ATmega8515(L) 142 interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty Interrupt, otherwise a new ...

Page 143

Data Reception – The USART Receiver Receiving Frames with Data Bits Receiving Frames with 9 Data Bits 2512G–AVR–03/05 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When ...

Page 144

ATmega8515(L) 144 (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and ninth bit, then data from buffer r18, UCSRA in r17, UCSRB in r16, UDR ...

Page 145

Receive Compete Flag and Interrupt Receiver Error Flags 2512G–AVR–03/05 The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one ...

Page 146

Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception ATmega8515(L) 146 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is ...

Page 147

Asynchronous Clock Recovery Asynchronous Data Recovery 2512G–AVR–03/05 The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- ure 68 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times ...

Page 148

Asynchronous Operational Range ATmega8515(L) 148 Figure 70 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 70. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X ...

Page 149

Multi-processor Communication Mode 2512G–AVR–03/05 Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table 62. ...

Page 150

Using MPCM ATmega8515(L) 150 The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular Slave ...

Page 151

Accessing UBRRH/UCSRC Registers Write Access 2512G–AVR–03/05 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the ...

Page 152

Read Access ATmega8515(L) 152 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled ...

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USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA 2512G–AVR–03/05 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART Receive ...

Page 154

USART Control and Status Register B – UCSRB ATmega8515(L) 154 This bit is set if the next character in the receive buffer had a Frame Error when received. For example, when the first stop bit of the next character in ...

Page 155

USART Control and Status Register C – UCSRC 2512G–AVR–03/05 Writing this bit to one enables the USART Transmitter. The Transmitter will override nor- mal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to ...

Page 156

ATmega8515(L) 156 Table 64. UPM Bits Settings UPM1 UPM0 • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The ...

Page 157

USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting 2512G–AVR–03/05 Bit URSEL – – Read/Write R R/W R/W R/W Initial Value The ...

Page 158

Table 68. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 ...

Page 159

Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 ...

Page 160

Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

Page 161

Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 ...

Page 162

Analog Comparator Analog Comparator Control and Status Register – ACSR ATmega8515(L) 162 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than ...

Page 163

Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana- log Comparator interrupt is activated. When written logic zero, the interrupt ...

Page 164

Boot Loader Support – Read-While-Write Self-Programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections ATmega8515(L) 164 The Boot Loader Support provides a real Read-While-Write Self-Programming mecha- nism for ...

Page 165

RWW – Read-While-Write Section NRWW – No Read-While-Write Section 2512G–AVR–03/05 Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write sec- tion” refers to ...

Page 166

Boot Loader Lock bits ATmega8515(L) 166 (1) Figure 73. Memory Sections Program Memory BOOTSZ = '11' $0000 Application Flash Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ ...

Page 167

Entering the Boot Loader Program 2512G–AVR–03/05 Table 74. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Note: 1. “1” means unprogrammed, “0” means programmed Table ...

Page 168

Store Program memory Control Register – SPMCR ATmega8515(L) 168 The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations. Bit SPMIE RWWSB – Read/Write R Initial Value 0 ...

Page 169

Addressing the Flash During Self- Programming 2512G–AVR–03/05 the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase SPM instruction is executed within four clock cycles. The ...

Page 170

Self-Programming the Flash ATmega8515(L) 170 Figure 74. Addressing the Flash during SPM BIT 15 ZPCMSB Z - REGISTER PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE Notes: 1. The different variables used in Figure 74 are ...

Page 171

Performing Page Erase by SPM Filling the Temporary Buffer (page loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self- Programming 2512G–AVR–03/05 To execute Page Erase, set up the address ...

Page 172

Setting the Boot Loader Lock bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software ATmega8515(L) 172 To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to ...

Page 173

Preventing Flash Corruption Programming Time for Flash when using SPM Simple Assembly Code Example for a Boot Loader 2512G–AVR–03/05 During periods of low V the Flash program can be corrupted because the supply volt- CC, age is too low for ...

Page 174

ATmega8515(L) 174 ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcallDo_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop r1, Y+ ldi spmcrval, (1<<SPMEN) rcallDo_spm adiw ...

Page 175

ATmega8515 Boot Loader Parameters 2512G–AVR–03/05 ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed ...

Page 176

ATmega8515(L) 176 Table 80. Explanation of Different Variables used in Figure 74 and the Mapping to the (1) Z-pointer Corresponding Variable Z-value PCMSB 11 PAGEMSB 4 ZPCMSB Z12 ZPAGEMSB Z5 PCPAGE PC[11:5] Z12:Z6 PCWORD PC[4:0] Z5:Z1 Note: 1. Z15:Z13: always ...

Page 177

Memory Programming Program and Data Memory Lock bits 2512G–AVR–03/05 The ATmega8515 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 82. The Lock bits can only ...

Page 178

Fuse bits ATmega8515(L) 178 Table 82. Lock Bit Protection Modes Memory Lock bits Protection Type No restrictions for SPM or LPM accessing the Boot Loader section SPM is not allowed to write to the ...

Page 179

Latching of Fuses Signature Bytes Calibration Byte Calibration Byte 2512G–AVR–03/05 Table 84. Fuse Low Byte Fuse Low Byte Bit no Description Brown-out Detector trigger BODLEVEL 7 level BODEN 6 Brown-out Detector enable SUT1 5 Select start-up time SUT0 4 Select ...

Page 180

Parallel Programming Parameters, Pin Mapping, and Commands Signal Names ATmega8515(L) 180 This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses are assumed to be ...

Page 181

Table 86. Pin Values used to Enter Programming Mode Pin PAGEL XA1 XA0 BS1 Table 87. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by ...

Page 182

Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase ATmega8515(L) 182 The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5 V between Set RESET to “0”, wait for at ...

Page 183

Programming the Flash 2512G–AVR–03/05 The Flash is organized in pages, see Table 89 on page 181. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. ...

Page 184

ATmega8515(L) 184 3. Wait until RDY/BSY goes high. (See Figure 77 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, ...

Page 185

Programming the EEPROM 2512G–AVR–03/05 Figure 77. Programming the Flash Waveforms $10 ADDR. LOW DATA LOW DATA HIGH DATA XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: “XX” is don’t care. The letters ...

Page 186

Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits ATmega8515(L) 186 Figure 78. Programming the EEPROM Waveforms $11 ADDR. HIGH ADDR. LOW DATA XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET ...

Page 187

Programming the Lock bits Reading the Fuse and Lock bits 2512G–AVR–03/ Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 ...

Page 188

Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics ATmega8515(L) 188 Figure 80. Mapping Between BS1, BS2, and the Fuse- and Lock bits During Read Fuse Low Byte Lock Bits Fuse High Byte BS2 The algorithm for reading ...

Page 189

Figure 82. Parallel Programming Timing, Loading Sequence with Timing (1) Requirements LOAD ADDRESS LOAD DATA (LOW BYTE) (LOW BYTE) XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 81 (i.e. t ...

Page 190

ATmega8515(L) 190 Table 91. Parallel Programming Characteristics, V Symbol Parameter t XTAL1 Low to WR Low XLWL t XTAL1 Low to PAGEL high XLPH t PAGEL low to XTAL1 high PLXH t BS1 Valid before PAGEL High BVPH t PAGEL ...

Page 191

Serial Downloading Serial Programming Pin Mapping 2512G–AVR–03/05 Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). ...

Page 192

Serial Programming Algorithm Data Polling Flash ATmega8515(L) 192 When writing serial data to the ATmega8515, data is clocked on the rising edge of SCK. When reading data from the ATmega8515, data is clocked on the falling edge of SCK. See ...

Page 193

Data Polling EEPROM 2512G–AVR–03/05 When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the ...

Page 194

Table 94. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable Chip Erase 1010 1100 0010 H000 Read Program memory 0100 H000 Load Program memory Page Write Program memory 0100 1100 Page 1010 0000 Read EEPROM Memory 1100 ...

Page 195

Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55qC to +125qC Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating ...

Page 196

DC Characteristics (Continued -40qC to 85qC 2.7V to 5.5V (Unless Otherwise Noted Symbol Parameter Power Supply Current I CC (5) Power-down mode Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input ...

Page 197

External Clock Drive Waveforms External Clock Drive 2512G–AVR–03/05 Figure 86. External Clock Drive Waveforms V IH1 V IL1 Table 95. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time ...

Page 198

SPI Timing Characteristics ATmega8515(L) 198 See Figure 87 and Figure 88 for details. Table 97. SPI Timing Parameters Description Mode 1 SCK period Master 2 SCK high/low Master 3 Rise/Fall time Master 4 Setup Master 5 Hold Master 6 Out ...

Page 199

Figure 88. SPI Interface Timing Requirements (Slave Mode SCK (CPOL = 0) SCK (CPOL = MOSI MSB (Data Input) 15 MISO MSB (Data Output) ATmega8515( ... LSB ... ...

Page 200

External Data Memory Timing Table 98. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL Address Hold ...

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