ISPLSI2128VE-250LQ160 Lattice Semiconductor Corp., ISPLSI2128VE-250LQ160 Datasheet
ISPLSI2128VE-250LQ160
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ISPLSI2128VE-250LQ160 Summary of contents
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... Interconnectivity • LEAD-FREE PACKAGE OPTIONS Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions) RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock I I/O 1 ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A Active ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Propagation Delay Clock Frequency with Internal Feedback max f – 4 Clock Frequency ...
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External Timing Parameters 3 TEST PARAMETER # COND. t pd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t grp 22 GRP Delay GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t grp 22 GRP Delay GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc t 4ptbpr 24 4 ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...
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Power Consumption Power consumption in the ispLSI 2128VE device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 350 300 250 ...
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Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of ...
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Signal Locations ...
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I/O Locations 208 176 Signal fpBGA TQFP PQFP ...
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Signal Configuration ispLSI 2128VE 208-Ball fpBGA Signal Diagram I/O I/O I I/O I I/O I/O I ...
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Pin Configuration ispLSI 2128VE 176-Pin TQFP Pinout Diagram I/O 113 1 VCC 2 3 I/O 114 4 I/O 115 5 I/O 116 6 I/O 117 7 I/O 118 8 I/O 119 I/O 120 10 I/O 121 11 ...
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Pin Configuration ispLSI 2128VE 160-Pin PQFP Pinout Diagram 1 I/O 113 2 VCC 3 I/O 114 4 I/O 115 5 I/O 116 I/O 117 6 I/O 118 7 8 I/O 119 9 I/O 120 10 I/O 121 11 I/O 122 ...
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Signal Configuration ispLSI 2128VE 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ ...
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Pin Configuration ispLSI 2128VE 100-Pin TQFP Pinout Diagram RESET 11 VCC ...
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Part Number Description ispLSI 2128VE Device Family Device Number Speed f 250 = 250 MHz max f 180 = 180 MHz max* f 135 = 135 MHz max f 100 = 100 MHz max *Use ispLSI 2128VE-250 for new designs ...
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Ordering Information (Cont.) Conventional Packaging (Cont.) FAMILY fmax (MHz) tpd (ns) 135 7.5 ispLSI 135 7.5 Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 250 4.0 250 4.0 250 4.0 135 7.5 ispLSI 135 7.5 135 7.5 100 10 ...