MC74HC175N Motorola, MC74HC175N Datasheet

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MC74HC175N

Manufacturer Part Number
MC74HC175N
Description
Quad D flip-flop with common clock and reset
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
inputs, and separate D inputs. Reset (active–low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
10/95
INPUTS
Motorola, Inc. 1995
DATA
The MC54/74HC175 is identical in pinout to the LS175. The device inputs
This device consists of four D flip–flops with common Reset and Clock
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates
CLOCK
D0
D1
D2
D3
RESET
12
13
9
4
5
1
PIN 16 = V CC
PIN 8 = GND
LOGIC DIAGRAM
10
15
14
11
2
3
7
6
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
NONINVERTING
INVERTING
OUTPUTS
AND
1
REV 6
16
MC54/74HC175
16
16
1
Reset Clock
1
RESET
H
H
H
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
L
ORDERING INFORMATION
1
GND
Q0
Q0
Q1
Q1
D0
D1
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
X
L
1
2
3
4
5
6
7
8
CERAMIC PACKAGE
D
X
H
X
PLASTIC PACKAGE
L
SOIC PACKAGE
CASE 751B–05
CASE 620–10
CASE 648–08
16
15
14
13
12
10
11
9
No Change
N SUFFIX
D SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
Outputs
Q
H
L
L
V CC
Q3
Q3
D3
D2
Q2
Q2
CLOCK
Q
H
H
L

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MC74HC175N Summary of contents

Page 1

... Chip Complexity 166 FETs or 41.5 Equivalent Gates LOGIC DIAGRAM 9 CLOCK DATA 11 INPUTS RESET PIN PIN 8 = GND 10/95 Motorola, Inc. 1995 INVERTING 6 Q1 AND Q2 NONINVERTING OUTPUTS MC54/74HC175 J SUFFIX CERAMIC PACKAGE 16 CASE 620–10 ...

Page 2

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î Î Î Î ...

Page 3

... NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... MC54/74HC175 90% CLOCK 50% 10 1/f max t PLH t PHL 90 50% 10% t TLH t THL Figure 1. CLOCK MOTOROLA SWITCHING WAVEFORMS V CC RESET GND Q Q CLOCK VALID DATA 50% Figure 3. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 4 ...

Page 5

... D0 9 CLOCK RESET High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM MC54/74HC175 MOTOROLA ...

Page 6

... 0.25 (0.010) –A – –T – SEATING PLANE 0.25 (0.010 MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V –B – 0.25 (0.010 SUFFIX PLASTIC PACKAGE CASE 648–08 ...

Page 7

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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