MX29LV800BBTC-70 Macronix International Co., MX29LV800BBTC-70 Datasheet
MX29LV800BBTC-70
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MX29LV800BBTC-70 Summary of contents
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FEATURES • Extended single - supply voltage range 2.7V to 3.6V • 1,048,576 x 8/524,288 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 70/90ns • Low ...
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PIN CONFIGURATIONS 44 SOP(500 mil) 44 RY/BY A18 3 42 A17 CE# ...
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BLOCK STRUCTURE TABLE 1: MX29LV800BT SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes ...
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TABLE 2: MX29LV800BB SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 16Kbytes 8Kwords SA1 8Kbytes 4Kwords SA2 8Kbytes 4Kwords SA3 32Kbytes 16Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes 32Kwords SA9 ...
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BLOCK DIAGRAM CONTROL CE# OE# INPUT WE# LOGIC RESET# ADDRESS LATCH A0-A18 AND BUFFER Q0-Q15/A-1 P/N:PM1062 MX29LV800BT/BB PROGRAM/ERASE HIGH VOLTAGE MX29LV800BT/BB FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 WRITE ...
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AUTOMATIC PROGRAMMING The MX29LV800BT/BB is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time ...
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VID, as shown in table 5. To verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest or- der address bit (see Table 1 and ...
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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29LV800BT/ BB) MX29LV800BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and ...
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TABLE 4-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Device size (2 N bytes) Flash device interface code (refer to the CFI publication 100) Maximum number of bytes in multi-byte write (not ...
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TABLE 5. MX29LV800BT/BB COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Sector Protect Word 4 555H AAH 2AAH Verify ...
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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...
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Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus ...
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TABLE 7. SILICON ID CODE Pins A0 Manufacture code Word VIL Byte VIL Device code Word VIH for MX29LV800BT Byte VIH Device code Word VIH for MX29LV800BB Byte VIH Sector Protection Word X Verification Byte X READING ARRAY DATA The ...
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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...
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Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a ...
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During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system ...
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If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase ...
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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. DATA# polling and Toggle Bit are valid after the initial sector ...
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Performing a read operation with A1=VIH, it will produce a logical "1" for the protected sector. CHIP UNPROTECTED The MX29LV800BT/BB also features the chip unpro- tected mode, so that all sectors are unprotected after chip unprotected is completed ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance TABLE 9. DC CHARACTERISTICS Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ILO Output Leakage ...
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AC CHARACTERISTICS TA = -40 TABLE 10. READ OPERATIONS SYMBOLPARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay tDF OE# High to Output Float (Note1) tOEH Output ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST SWITCHING TEST WAVEFORMS 3. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1062 MX29LV800BT/BB CL ...
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FIGURE 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1062 MX29LV800BT/BB tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 25 tDF ...
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AC CHARACTERISTICS TA = -40 TABLE 11. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL Read ...
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AC CHARACTERISTICS TA = -40 TABLE 12. Alternate CE# Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...
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FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1062 MX29LV800BT/BB ADD Valid tAH tWPH tWP tCWC tCH tDS tDH DIN 28 REV. ...
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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...
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FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No ...
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FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# CE# tWS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates ...
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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by DATA# polling and toggle bit checking after ...
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FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H ...
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by DATA# polling and toggle bit ...
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FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address ...
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FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART Note the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the delay time must be put into consideration. 2. Delay timing: 1.5ms ...
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FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPROTECTED TIMING WAVEFORM (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Protect or Chip Unprotect Data 60h 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0. ...
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FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control 12V 3V A9 tVLHT 12V 3V OE# tVLHT WE# CE# Data A18-A12 P/N:PM1062 MX29LV800BT/BB tWPP 1 tOESP Sector Address 38 Verify tVLHT 01H F0H tOE REV. 1.3, DEC. 20, ...
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FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control) No PLSCNT=32? Yes Device Failed P/N:PM1062 MX29LV800BT/BB START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read from ...
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FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM1062 MX29LV800BT/BB START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector address ...
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FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM1062 MX29LV800BT/BB START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? Yes ...
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FIGURE 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) A1 12V Vcc 3V A9 tVLHT A6 12V Vcc 3V OE# tVLHT WE# CE# Data A18-A12 Notes: tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min, ...
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FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1062 MX29LV800BT/BB START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL,A6=1 Activate WE# Pulse Time ...
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WRITE OPERATION STATUS FIGURE 18. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1062 MX29LV800BT/BB Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? No No ...
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FIGURE 19. TOGGLE BIT ALGORITHM NO Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1062 MX29LV800BT/BB Start Read Q7-Q0 Read Q7-Q0 (Note ...
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FIGURE 20. DATA# Polling Timings (During Automatic Algorithms) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# DQ7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, ...
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FIGURE 21. Toggle Bit Timings (During Automatic Algorithms) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...
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TABLE 13. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET# Pulse Width (During Automatic ...
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AC CHARACTERISTICS TABLE 14. WORD/BYTE CONFIGURATION (BYTE#) Parameter Description JEDEC Std tELFL/tELFH CE# to BYTE# Switching Low or High tFLQZ BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active FIGURE 23. BYTE# TIMING WAVEFORM FOR ...
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FIGURE 24. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 FIGURE 25. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# WE# BYTE# P/N:PM1062 MX29LV800BT/BB tELFH DOUT (Q0-Q14) DOUT VA (Q15) ...
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TABLE 15. TEMPORARY SECTOR UNPROTECTED Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotected Note: Not 100% tested FIGURE 26. TEMPORARY SECTOR UNPROTECTED TIMING DIAGRAM 12V RESET Vcc ...
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FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. P/N:PM1062 MX29LV800BT/BB Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH VID=11.5V~12.5V 2. ...
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FIGURE 29. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL ...
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TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Byte Mode Word Mode Erase/Program Cycles Note: 1. Not 100% Tested, Excludes external system level over head. ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX29LV800BTMC-70 70 MX29LV800BBMC-70 70 MX29LV800BTMC-90 90 MX29LV800BBMC-90 90 MX29LV800BTTC-70 70 MX29LV800BBTC-70 70 MX29LV800BTTC-90 90 MX29LV800BBTC-90 90 MX29LV800BTXBC-70 70 MX29LV800BTXBC-90 90 MX29LV800BBXBC-70 70 MX29LV800BBXBC-90 90 MX29LV800BTMI-70 70 MX29LV800BBMI-70 70 MX29LV800BTMI-90 90 MX29LV800BBMI-90 90 MX29LV800BTTI-70 70 MX29LV800BBTI-70 70 MX29LV800BTTI-90 90 MX29LV800BBTI-90 90 MX29LV800BTXBI-70 70 MX29LV800BTXBI-90 90 MX29LV800BBXBI-70 70 MX29LV800BBXBI-90 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA ...
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... PART NO. ACCESS TIME (ns) MX29LV800BTXEC-70 70 MX29LV800BTXEC-90 90 MX29LV800BBXEC-70 70 MX29LV800BBXEC-90 90 MX29LV800BTXEI-70 70 MX29LV800BTXEI-90 90 MX29LV800BBXEI-70 70 MX29LV800BBXEI-90 90 MX29LV800BTTC-70G 70 MX29LV800BBTC-70G 70 MX29LV800BTTC-90G 90 MX29LV800BBTC-90G 90 MX29LV800BTXBC-70G 70 MX29LV800BTXBC-90G 90 MX29LV800BBXBC-70G 70 MX29LV800BBXBC-90G 90 MX29LV800BTTI-70G 70 MX29LV800BBTI-70G 70 MX29LV800BTTI-90G 90 MX29LV800BBTI-90G 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA ...
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PART NO. ACCESS TIME (ns) MX29LV800BTXBI-70G 70 MX29LV800BTXBI-90G 90 MX29LV800BBXBI-70G 70 MX29LV800BBXBI-90G 90 MX29LV800BTXEC-70G 70 MX29LV800BTXEC-90G 90 MX29LV800BBXEC-70G 70 MX29LV800BBXEC-90G 90 MX29LV800BTXEI-70G 70 MX29LV800BTXEI-90G 90 MX29LV800BBXEI-70G 70 MX29LV800BBXEI-90G 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA) 30 ...
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PACKAGE INFORMATION P/N:PM1062 MX29LV800BT/BB 58 REV. 1.3, DEC. 20, 2004 ...
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P/N:PM1062 MX29LV800BT/BB 59 REV. 1.3, DEC. 20, 2004 ...
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CSP (for MX29LV800BTXBC/BTXBI/BBXBC/BBXBI) P/N:PM1062 MX29LV800BT/BB 60 REV. 1.3, DEC. 20, 2004 ...
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CSP (for MX29LV800BTXEC/BTXEI/BBXEC/BBXEI) P/N:PM1062 MX29LV800BT/BB 61 REV. 1.3, DEC. 20, 2004 ...
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REVISION HISTORY Revision No. Description 1 corrected data retention information 2. Removed "Advanced Information" 1 corrected CFI Query command address 1.2 1. Added MX29LV800BTXEI/BBXEI-70/90 & MX29LV800BTXEC/ BBXEC/BTXEI/BBXEI-70G/90G in Ordering Information 1 corrected tRC definition ...
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... MX29LV800BT/BB MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...